Serial vs parallel signaling (SerDes): Exercises — Hinglish deep dive

6.3.12 · D4 · Hardware › Interconnects, Buses & SoC › Serial vs parallel signaling (SerDes)

Yeh page SerDes ke liye ek self-test ladder hai. Har problem apna level batata hai — sirf ek word pehchaanna (L1) se lekar ideas ko end-to-end combine karna (L5) tak. Pehle khud solve karo, phir collapsible solution kholna. Har level ke baad ek [!mistake] callout hai jo woh trap dikhata hai jo sahi lagta hai par hota nahi.

Har quantity pehli baar appear hone par define ki gayi hai. Pehle ke notes se kuch assume nahi kiya gaya.

Level 1 — Recognition

Kya tum pieces ka naam le sakte ho aur units padh sakte ho?

Exercise 1.1

Ek-ek sentence mein batao ki Serializer kya karta hai aur Deserializer kya karta hai, aur yeh bhi batao ki inmen se kaun transmitter par rehta hai.

Recall Solution

Serializer (transmitter): chip ke andar $n$ wires par side-by-side baithey $n$ parallel bits leta hai aur unhe ek single line par ek-ek karke bahar bhejta hai — jaise cards ki stack ko ek slot se through karna.
Deserializer (receiver): bits ki us single stream ko dekhta hai aur original side-by-side group of $n$ bits wapas rebuild karta hai.
Serializer transmitter par rehta hai (woh serialize karta hai = bhejna se pehle serial banata hai). Block diagram ke liye Serial vs parallel signaling (SerDes) dekho.

Exercise 1.2

Ek serial link symbol rate $R_{s} = 5$ Gbaud par symbols bhejta hai aur NRZ use karta hai — ek scheme jahan har symbol sirf ek voltage hoti hai (high = 1, low = 0), toh woh exactly 1 bit per symbol carry karta hai. Bit period $T_{bi t}$ kya hai, yaani woh time jitna ek bit wire par occupy karta hai?

Recall Solution

Bit period us rate ka reciprocal hai jis par bits guzarte hain. Kyunki yahan har symbol ek bit hai, bit rate symbol rate ke barabar hai: $5 \times 1 0^{9}$ bits per second. $T_{bi t} = \frac{1}{R _{s}} = \frac{1}{5 \times 1 0 ^{9} s ^{- 1}} = 2 \times 1 0^{- 10} s = 200 ps$ Reciprocal kyun? Agar 5 billion bits har second guzarte hain, toh har bit ko $1/5, 000, 000, 000$ second milta hai — ek second ko saare bits mein fairly divide karo.

Exercise 1.3

Har problem ko woh parallel-bus physics effect match karo jiska woh naam leta hai: (a) alag-alag wires par bits thodi alag timing par pohunchti hain; (b) ek switching wire apne neighbour par noise push karta hai; (c) bahut saare wires saath mein switch karke radio waves radiate karte hain.

Recall Solution

(a) = Skew — wires ke beech ek timing misalignment.
(b) = Crosstalk — ek aggressor aur victim wire ke beech capacitive/inductive coupling.
(c) = EMI (electromagnetic interference) — bus ek antenna ki tarah act karta hai. Yeh thi woh teen physics walls jinhone industry ko parallel se serial ki taraf dhakela.

Level 2 — Application

Numbers ko note ke formulas mein plug karo.

Exercise 2.1

Ek PCB (printed circuit board) par ek parallel bus ki shortest aur longest wire ke beech trace mismatch $ℓ = 8$ mm hai. Signals board se $v = 1.8 \times 1 0^{8}$ m/s ki speed se guzarte hain (light ki speed ka lagbhag $0.6$ guna, FR-4 board material ke liye typical). Skew $Δ t_{s k e w}$ — woh extra travel time jo extra length ki wajah se hoti hai — calculate karo.

Recall Solution

Skew sirf extra distance divided by speed hai (time = distance / speed): $Δ t_{s k e w} = \frac{ℓ}{v} = \frac{8 \times 1 0 ^{- 3} m}{1.8 \times 1 0 ^{8} m/s} = 4.44 \times 1 0^{- 11} s \approx 44.4 ps$ Yeh formula kyun? Jo wire 8 mm lambi hai woh signal ko us extra copper ko cross karne mein extra time lagati hai. Woh delayed bit apne siblings se late pohunchta hai — exactly woh skew jo receiver ko tolerate karna hota hai.

Exercise 2.2

Exercise 2.1 continue karo. Receiver ko setup time $t_{se t u p} = 20$ ps chahiye (data sampling clock edge se pehle stable hona chahiye) aur hold time $t_{h o l d} = 15$ ps chahiye (data edge ke baad stable rehna chahiye). $T_{c l k}$ ko clock period maano (do consecutive sampling clock edges ke beech ka time, jaise upar intuition callout mein bataya gaya). Parent note ke rule ko use karke $T_{c l k} \geq Δ t_{s k e w} + t_{se t u p} + t_{h o l d},$ is parallel bus ki maximum clock frequency $f_{ma x}$ nikalo.

Recall Solution

Pehle minimum clock period add karo. Clock itni fast nahi tick kar sakti ki sabhi bits pohunchne (skew), settle hone (setup) aur tikne (hold) ka time se zyada ho: $T_{c l k, m i n} = 44.4 + 20 + 15 = 79.4 ps = 7.94 \times 1 0^{- 11} s$ Sabse fast clock smallest allowed period ka reciprocal hai: $f_{ma x} = \frac{1}{T _{c l k, m i n}} = \frac{1}{7.94 \times 1 0 ^{- 11}} \approx 1.26 \times 1 0^{10} Hz \approx 12.6 GHz$ Upper limit kyun? Clock ko isse fast karo aur period $79.4$ ps se neeche chali jaayegi — clock edge pehle pohunch jaayegi har bit ke settle hone se, toh receiver garbage sample karta hai.

Exercise 2.3

Ek serial lane symbol rate $R_{s} = 8.0$ GT/s (gigatransfers per second) par run karti hai aur 128b/130b encoding use karti hai — har 128 real data bits ke liye wire actually 130 bits carry karta hai (2 extra bits block boundaries mark karte hain). NRZ ka matlab $b = 1$ bit per symbol hai. Usable data rate $R_{d a t a}$ calculate karo.

Recall Solution

Note ka formula use karo $R_{d a t a} = R_{s} \cdot η \cdot b$ , jahan efficiency $η$ transmitted bits ka woh fraction hai jo real data hai: $η = \frac{128}{130} \approx 0.9846$ $R_{d a t a} = 8.0 \times 1 0^{9} \times \frac{128}{130} \times 1 \approx 7.877 \times 1 0^{9} bps \approx 7.877 Gbps$ $η < 1$ se multiply kyun? Wire par har bit aapka payload nahi hota — har 130 mein se 2 "packaging" hain. Tum sirf $128/130$ fraction rakh sakte ho. Yeh 8b/10b Encoding logic se match karta hai, bas leaner overhead ke saath. Yeh ek PCIe Protocol Gen3 link ki per-lane rate hai.

Level 3 — Analysis

Compare karo, judge karo, aur "kyun" explain karo.

Exercise 3.1

Exercise 2.1 ka skew lo ( $Δ t_{s k e w} = 44.4$ ps). Skew ko clock period ke percentage ke roop mein express karo teen clock speeds par: $133$ MHz, $1$ GHz, aur $5$ GHz. Batao kis speed par skew unmanageable ho jaata hai (rule of thumb: period ke $\sim 10%$ se upar).

Neeche ka figure exactly yahi plot karta hai. Iska horizontal axis teen clock speeds list karta hai ( $133$ MHz, $1$ GHz, $5$ GHz); vertical axis "skew as % of clock period" hai. Har bar wahi same $44.4$ ps skew hai jo us speed ki shrinking clock period ke against measure ki gayi hai. Dashed horizontal line $10%$ danger threshold mark karti hai. Do bars black hain (safe); red bar $5$ GHz case hai jo danger line ke upar jaata hai — woh red bar "skew wall" hai.

Figure — Serial vs parallel signaling (SerDes)

Recall Solution

Period $T = 1/ f$ , phir percentage $= Δ t_{s k e w} / T \times 100%$ .

133 MHz: $T = 1/ (133 \times 1 0^{6}) = 7.52$ ns $= 7519$ ps → $44.4/7519 = 0.59%$ . Trivial.
1 GHz: $T = 1000$ ps → $44.4/1000 = 4.44%$ . Noticeable hone laga.
5 GHz: $T = 200$ ps → $44.4/200 = 22.2%$ . Unmanageable — clock ka ek-paanchva se zyada hissa akele skew khaa jaata hai. Analysis: wahi physical mismatch low speed par harmless hai aur high speed par fatal — kyunki clock period shrink hoti hai jabki skew (fixed board geometry se set) nahi hota. Figure mein, red $5$ GHz bar dashed $10%$ line se upar tower karta hai — yahi woh physics wall hai jisne wide parallel buses ko khatam kiya. Serial isse bachta hai kyunki iske paas ek data lane hai, toh wire-to-wire alignment lose karne ki koi baat nahi.

Exercise 3.2

Do designs chips ke beech data move karte hain:

Design A: ek 32-bit parallel bus $400$ MHz par clocked, 1 bit per wire per cycle.
Design B: ek single serial lane $16$ GT/s NRZ par $η = 0.97$ ke saath (64b/66b encoding).

Kaun zyada raw throughput deta hai, aur — skew se argue karte hue — kaun higher speeds tak scale karta hai?

Recall Solution

Abhi throughput:

Design A: $32 bits \times 400 \times 1 0^{6} cycles/s = 1.28 \times 1 0^{10} = 12.8$ Gbps.
Design B: $16 \times 1 0^{9} \times 0.97 \times 1 = 1.552 \times 1 0^{10} = 15.52$ Gbps.

Design B already jeet gaya ( $15.52 > 12.8$ Gbps) ek lane vs 32 wires par.

Scaling argument: B ko beat karne ke liye, Design A ko apna 400 MHz clock raise karna hoga. Lekin uske 32 wires mein har ek skew carry karta hai; jaise 3.1 mein dikhaya, jab period skew ke paas aa jaati hai, sampling fail ho jaati hai. Design A kuch GHz ke around skew wall hit karta hai aur 32 pins ke crosstalk aur EMI ka cost bhi hai. Design B mein koi wire-to-wire skew nahi (ek lane) aur woh Differential Signaling ke zariye noise ko common-mode ki tarah reject karta hai — toh woh climb karta rehta hai (Gen4, Gen5...). Serial scales; wide parallel nahi karta.

Level 4 — Synthesis

Kai ideas ko ek end-to-end result mein combine karo.

Exercise 4.1

Ek 8:1 serializer slow clock $f_{l o w} = 1.25$ GHz par 8 parallel bits load karta hai aur unhe ek serial line par shift out karta hai. (a) Internal PLL ko kitna fast clock $f_{hi g h}$ chahiye? (b) Serial bit period $T_{bi t}$ kya hai? (c) Agar input byte 0xB4 = 10110100 hai (MSB first), toh poore byte ke liye output high/low intervals list karo.

Recall Solution

(a) Ek serializer ek slow-clock period mein saare 8 bits bhejta hai, toh use 8 guna fast shift karna hoga: $f_{hi g h} = 8 \times f_{l o w} = 8 \times 1.25 \times 1 0^{9} = 1.0 \times 1 0^{10} = 10 GHz$ (b) Har fast-clock cycle mein ek bit: $T_{bi t} = \frac{1}{f _{hi g h}} = \frac{1}{10 \times 1 0 ^{9}} = 1.0 \times 1 0^{- 10} s = 100 ps$ Check: 8 bits $\times$ 100 ps $= 800$ ps $= 1/ (1.25 GHz)$ — exactly ek slow period. ✓ (c) 10110100, 100 ps per bit, MSB first, (interval → bit → level) list kiya:

$0$ – $100$ ps → bit $1$ → High
$100$ – $200$ ps → bit $0$ → Low
$200$ – $300$ ps → bit $1$ → High
$300$ – $400$ ps → bit $1$ → High
$400$ – $500$ ps → bit $0$ → Low
$500$ – $600$ ps → bit $1$ → High
$600$ – $700$ ps → bit $0$ → Low
$700$ – $800$ ps → bit $0$ → Low

PLL kyun? Chip ki logic 1.25 GHz par comfortable hai, lekin wire ko bits 8× faster carry karni hain. PLL slow clock ko multiply karke woh 10 GHz clock manufacture karta hai — yahi woh engine hai jo ek wire ko aath ka kaam karne deta hai.

Exercise 4.2

Receiver ka equalizer signal clean karta hai, aur ek eye diagram "eye" dikhata hai — woh open region jahan signal safely high ya low hai — jo 4.1 ke 10 GHz link par $60$ ps wide hai. CDR (clock-data recovery) ko us eye ke andar sample karna hai. Maximum allowed sampling phase error $∣Δ ϕ ∣$ kya hai, aur kya $\pm 8$ ps tak lock karne wala CDR succeed karta hai?

Recall Solution

Safe window eye hai. Iske andar rehne ke liye, sampling point centre se zyada se zyada aadha eye width drift kar sakta hai (left ya right): $∣Δ ϕ ∣_{m a x} = \frac{60 ps}{2} = 30 ps$ $\pm 8$ ps tak lock karne wala CDR andar rahta hai: $8 < 30$ . ✓ Succeed karta hai $22$ ps ke margin ke saath. Eye ka aadha kyun? Maximum safety ke liye sample ko eye mein centre karo. Agar woh kisi bhi edge ki taraf aadhe se zyada drift kare, toh woh open region se bahar nikal jaata hai aur transition ke dauran sample karta hai — ek coin-flip bit. Parent note ka rule $∣Δ ϕ ∣ < T_{bi t} /2$ idealised case hai (full-width eye); eye diagram channel loss ke baad real narrower budget deta hai.

Level 5 — Mastery

Constraints ke under full end-to-end system reasoning.

Exercise 5.1

Tumhe do chips ke beech 100 Gbps usable data deliver karna hai. Do builds compare karo:

Serial build: identical PCIe-style lanes, har ek $8.0$ GT/s NRZ $η = 128/130$ ke saath (yaani $7.877$ Gbps usable, Exercise 2.3 se). Do wires per lane (differential pair).
Parallel build: ek single-ended wide bus $2.0$ GHz par, 1 bit per wire, ek wire each. (a) Kitne serial lanes chahiye? (b) 100 Gbps match karne ke liye kitne parallel wires chahiye? (c) Kaun kam physical wires use karta hai, aur deciding physics ka naam batao.

Recall Solution

(a) Target ko per-lane rate se divide karo, round up (tum lane ka fraction nahi khareed sakte): $N_{l an es} = ⌈ \frac{100 \times 1 0 ^{9}}{7.877 \times 1 0 ^{9}} ⌉ = ⌈ 12.7 ⌉ = 13 lanes$ Kyunki PCIe link widths powers of two mein aate hain, practice mein tum x16 link (16 lanes) deploy karoge. (b) Har parallel wire $2.0 \times 1 0^{9} = 2$ Gbps deta hai: $N_{w i r es} = ⌈ \frac{100 \times 1 0 ^{9}}{2.0 \times 1 0 ^{9}} ⌉ = 50 wires$ (c) Physical wire count:

Serial: $13$ lanes $\times 2$ wires $= 26$ wires.
Parallel: $50$ wires.

Serial jeet gaya ( $26 < 50$ ), aur parallel bus ke clock/strobe wires add karne par toh competition hi khatam. Deciding physics: har serial lane $8$ GT/s par cleanly run karta hai kyunki woh ek akela differential pair hai jisme koi wire-to-wire skew nahi, low crosstalk, aur cancelling EMI. Parallel bus $2$ GHz par stuck hai exactly kyunki 50 skewed, crosstalking, radiating wires ek faster clock share nahi kar sakte. Speed-per-wire, wire-count nahi, jo jeetta hai — same lesson jaise DDR pins add karne ke bajaye per-pin rates push karta hai.

Exercise 5.2

5.1 se $8.0$ GT/s NRZ par ek lane lo. Transmit crystal aur receive crystal $300$ ppm (parts per million — $300$ Hz drift per million Hz) se alag hain. (a) Dono ends raw symbol count mein kitne bits per second drift karte hain? (b) Ek paragraph mein explain karo kyun CDR ko continuously adjust karna chahiye na ki ek baar lock karna.

Recall Solution

(a) $300$ ppm ka drift matlab receiver ka rate ka idea $300/1 0^{6} = 3 \times 1 0^{- 4}$ fraction se off hai: $Δ R = R_{s} \times 300 \times 1 0^{- 6} = 8.0 \times 1 0^{9} \times 3 \times 1 0^{- 4} = 2.4 \times 1 0^{6} symbols/s = 2.4 Msymbol/s$ Receiver ka clock transmitter actually bhejne se $2.4$ million symbols per second zyada (ya kam) count karta hai. (b) Kyunki do crystals exactly same frequency par kabhi nahi chalte, ek sampling point jo abhi perfectly centred hai woh akele chhadne par $2.4$ million bit-widths per second slide karega — woh microseconds mein eye se bahar nikal jaayega aur uske baad har bit galat hogi. Toh CDR har incoming data edge ko dekhta hai, phase ko early ya late creep karte dekhta hai, aur apne local clock ko opposite direction mein nudge karta hai, baar baar. Yeh ek time ka alignment nahi balki ek servo loop hai jo transmitter ki frequency ko track karta hai jab tak link up hai — exactly woh behaviour jo parent note USB CDR ke liye describe karta hai.