Serial vs parallel signaling (SerDes): Foundations

Before you read the parent note Serial vs parallel signaling (SerDes), you must own the vocabulary it fires at you. We go one symbol at a time. Nothing is used before it is drawn.

1. A "bit" — the smallest thing we send

Picture a wire as a garden hose for electricity. We don't measure how much water — only whether the tap is on (high, $1$ ) or off (low, $0$ ).

Figure — Serial vs parallel signaling (SerDes)

Figure 1 — Vertical axis: voltage $V$ ; horizontal axis: time. The blue trace steps between the low level (" $0$ ", red dashed line) and the high level (" $1$ ", green dashed line). The orange arrow marks one bit — a single flat plateau at one level.

Look at the figure: the vertical axis is voltage (how "high" the electrical pressure is), the horizontal axis is time. A bit is one flat plateau at a level. The whole subject is just: how do we push these plateaus down a wire, quickly, without them getting scrambled?

Why the topic needs it: everything — bytes, buses, gigabits — is counted in bits.

2. Voltage $V$ and its rate of change $\frac{d V}{d t}$

When a bit flips from $0$ to $1$ , the voltage does not teleport — it ramps up. The steepness of that ramp is written $\frac{d V}{d t}$ .

Figure 2 — Two rising edges going from $0 V$ to $1 V$ . The orange edge climbs in a fraction of the time (steep, big $\frac{d V}{d t}$ ); the green edge climbs slowly (gentle, small $\frac{d V}{d t}$ ). Horizontal axis in picoseconds; vertical axis is voltage.

Why this tool and not another? We use a slope because the parent note's crosstalk formula, $V_{cr oss t a l k} \approx C_{m u t u a l} \frac{d V _{a g g r essor}}{d t}$ , says the trouble one wire causes its neighbour depends only on how fast the first wire's voltage is swinging, not on where it ends up. The slope is exactly the question "how fast?", so slope is the right tool. Steep orange edge in the figure = loud neighbour; gentle green edge = quiet neighbour.

3. Time units: nanoseconds and picoseconds

Why the topic needs it: signals live at these scales. Light itself only travels about $30 cm$ in $1 ns$ . When the parent says " $5 ps$ of skew," it means five trillionths of a second — and it still matters. Hold onto $1 ns = 1000 ps$ ; the parent uses it constantly.

4. The clock and its period $T_{c l k}$

Figure 3 — A blue square-wave clock. The red double-headed arrow spans exactly one period $T$ (one tick + one tock). Dotted grey lines mark the rising edges. Caption note: more ticks per second means a smaller $T$ , since $f = 1/ T$ .

Why reciprocal and not something else? "How many per second" and "how long is one" are literally the same fact seen from two sides — like "3 pizzas per hour" versus "20 minutes per pizza." Flipping one gives the other. This is why the parent writes both $f_{ma x} = \frac{1}{T _{c l k}}$ and $T_{c l k} = \frac{1}{f}$ : same idea, whichever is convenient.

5. A wire, its length $l$ , and how fast signals crawl

Why the topic needs it: a signal takes real time to run down a wire. The time to cross a trace of length $l$ is $t_{d e l a y} = \frac{l}{v} .$ This is just "time = distance ÷ speed," the same rule as a road trip. It is the seed of skew, coming next.

6. Many wires → skew $Δ t_{s k e w}$

Figure 4 — Two bits launched together at the dotted "both launched" line. The blue bit travels the short wire and its edge rises early; the red bit travels the longer wire and its edge rises late. The orange double-headed arrow between the two rising edges is the skew $Δ t_{s k e w}$ .

Why the topic needs it: skew is the whole reason parallel buses hit a wall. If two wires differ in length by $δ l$ , their arrival times differ by $Δ t_{s k e w} = \frac{δ l}{v} .$ Look at the figure: two bits launched together, one wire longer, so the red bit lands late. If the late bit hasn't settled when the clock samples, you read garbage. That is precisely why the parent compares $Δ t_{s k e w}$ against $T_{c l k}$ : a $28 ps$ skew is fine inside a $7500 ps$ period but fatal inside a $200 ps$ one.

7. Setup and hold — the sampling "quiet window"

That is why the parent's clock-limit reads $T_{c l k} \geq Δ t_{s k e w} + t_{se t u p} + t_{h o l d}$ : the period must fit the skew plus this quiet window. Every symbol in that formula is now defined.

8. Differential pair — two wires telling the same story

Figure 5 — Three stacked traces. Top (blue) = wire $+$ , middle (orange) = wire $-$ ; the two carry opposite data. A red noise bump lands on both at the same time. Bottom (green) = their difference: the opposite data doubles up while the shared noise bump cancels to nothing — clean recovered data.

Why the topic needs it: serial links send on a single differential pair. In the figure, noise hits both wires equally (grey bump on both), so it cancels in the difference — the receiver is deaf to it. That is why the parent claims serial "rejects crosstalk as common-mode noise." Common-mode = the part both wires share; the receiver ignores it and keeps only the opposite (differential) part.

9. Symbols, bits-per-symbol $b$ , and rates

Why $lo g_{2}$ and not plain counting? Each extra bit doubles the number of distinguishable levels ( $1$ bit → $2$ levels, $2$ bits → $4$ , $3$ bits → $8$ ). The function that undoes doubling — "how many doublings to reach this many levels?" — is exactly $lo g_{2}$ . That is why the parent's data-rate formula multiplies by $b$ .

Putting them together, the parent's serial rate reads $R_{d a t a} = R_{s} \cdot η \cdot b,$ now every letter has a meaning: symbols/sec $\times$ useful fraction $\times$ bits/symbol.

10. The PLL — a clock multiplier

Why the topic needs it: the serializer must shift bits out $8 \times$ faster than the parallel data arrives, so it needs an $8 \times$ clock. The PLL makes $f_{hi g h} = n \cdot f_{l o w}$ . That's the "Fast Clock Multiplication" step in the parent's serializer walk-through.

11. CDR and phase $ϕ$

Why sample in the middle? The edges are where the voltage is ramping and uncertain; the middle of a bit is the flat, confident plateau. The parent's rule $∣Δ ϕ ∣ < \frac{T _{bi t}}{2}$ just says: if your sampling point drifts more than half a bit away from the middle, you fall off into the neighbouring bit. Here $T_{bi t} = \frac{1}{R _{s}}$ is the time for one bit — same reciprocal trick as $T_{c l k}$ .

How these foundations feed the topic

Equipment checklist

Cover the right side and answer out loud; reveal to check.

What a bit is, physically on a wire

A single 0/1 value shown as a low/high voltage level.

The meaning of

\frac{d V}{d t}

The slope of a voltage edge — how fast the voltage is changing.

What

C_{m u t u a l}

is and its units

Mutual capacitance — how strongly two neighbouring wires couple electrically; measured in farads (pF/cm on a board).

How many picoseconds are in a nanosecond

1 ns = 1000 ps

The link between

f

and

T_{c l k}

They are reciprocals:

f = \frac{1}{T _{c l k}}

The period of a

5 GHz

clock

200 ps

(i.e.

0.2 ns

The difference between

Δ

and

δ

here

Both mean "a difference in" — capital

Δ

for a time gap, lower-case

δ

for a length gap.

How to turn wire-length mismatch into a time

Divide by propagation speed:

Δ t_{s k e w} = \frac{δ l}{v}

, with

v \approx 1.8 \times 1 0^{8} m/s

What skew is and why it caps parallel speed

The spread in arrival times across wires; when it approaches

T_{c l k}

you sample unsettled bits.

Why setup/hold time exists

The voltage must sit still just before and after the clock edge or the sample blurs.

Why a differential pair rejects noise

Noise hits both wires equally (common-mode) and cancels in their difference.

What

b

(bits per symbol) means, and why

lo g_{2}

b = lo g_{2} (levels)

; each extra bit doubles the number of levels.

The meaning of efficiency

η

The fraction

k / N

of transmitted bits that are real data (rest is encoding overhead).

What the PLL multiplier

n

does

Multiplies a slow clock into a fast one,

f_{hi g h} = n \cdot f_{l o w}

What CDR recovers, and where it samples

It recreates the clock from data edges and samples in the middle of each bit.

The CDR phase-error rule in words

Sampling phase must stay within half a bit period of the ideal point:

∣Δ ϕ ∣ < \frac{T _{bi t}}{2}

Recall Ready to advance?

If every reveal above felt automatic, go read the parent note Serial vs parallel signaling (SerDes) — you now own every symbol it uses. Then branch into Eye Diagrams, Equalization (CTLE, DFE), and DDR Memory Interface.