Foundations — Serial vs parallel signaling (SerDes)

6.3.12 · D1 · Hardware › Interconnects, Buses & SoC › Serial vs parallel signaling (SerDes)

Parent note Serial vs parallel signaling (SerDes) padhne se pehle, tumhare paas uski vocabulary honi chahiye. Hum ek symbol ek time pe lete hain. Kuch bhi use nahi hota jab tak draw na ho.

1. Ek "bit" — sabse chota cheez jo hum bhejte hain

Ek wire ko bijli ke liye garden hose samjho. Hum nahin maapte kitna paani — sirf yeh ki nala on hai (high, $1$) ya off (low, $0$).

Figure dekho: vertical axis voltage hai (electrical pressure kitni "high" hai), horizontal axis time hai. Ek bit ek level pe ek flat plateau hai. Poora subject bas yeh hai: hum in plateaus ko wire ke neeche kaise push karte hain, jaldi se, bina unhe scramble hue?

Yeh topic iske liye kyun zaroori hai: sab kuch — bytes, buses, gigabits — bits mein count hote hain.

2. Voltage $V$ aur iska change ki rate $\frac{dV}{dt}$

Jab ek bit $0$ se $1$ pe flip hoti hai, voltage teleport nahi hoti — yeh ramp karti hai upar. Us ramp ki steepness $\frac{dV}{dt}$ likhi jaati hai.

Yeh tool kyun aur koi nahi? Hum slope use karte hain kyunki parent note ka crosstalk formula, $V_{crosstalk}\approx C_{mutual}\frac{d{V}_{aggressor}}{dt}$, kehta hai ki ek wire apne neighbour ko jo trouble deti hai woh sirf is par depend karta hai ki pehli wire ki voltage kitni tezi se swing kar rahi hai, na ki woh kahan end hoti hai. Slope bilkul wahi sawaal hai "kitni tezi se?", isliye slope sahi tool hai. Figure mein steep orange edge = loud neighbour; gentle green edge = quiet neighbour.

3. Time units: nanoseconds aur picoseconds

Yeh topic iske liye kyun zaroori hai: signals in scales pe jeete hain. Khud light sirf lagbhag $30\text{cm}$ chalti hai $1\text{ns}$ mein. Jab parent kehta hai "$5\text{ps}$ of skew," matlab five trillionths of a second — aur yeh phir bhi matter karta hai. $1\text{ns}=1000\text{ps}$ yaad rakho; parent ise baar baar use karta hai.

4. Clock aur uska period $T_{clk}$

Reciprocal kyun aur kuch nahi? "Ek second mein kitne" aur "ek kitna lamba hai" literally ek hi fact hai do sides se dekha gaya — jaise "3 pizzas per hour" versus "20 minutes per pizza." Ek ko flip karo toh doosra milta hai. Isliye parent dono $f_{max}=\frac{1}{T_{clk}}$ aur $T_{clk}=\frac{1}{f}$ likhta hai: same idea, jo convenient ho.

5. Ek wire, uski length $l$, aur signals kitni dheere chalte hain

Yeh topic iske liye kyun zaroori hai: ek signal ko wire ke neeche jaane mein real time lagta hai. Length $l$ ka ek trace cross karne ka time hai $t_{delay}=\frac{l}{v}.$ Yeh bas "time = distance ÷ speed" hai, road trip wala same rule. Yeh skew ka seed hai, jo aage aata hai.

6. Bahut saari wires → skew $\Delta t_{skew}$

Yeh topic iske liye kyun zaroori hai: skew hi poori wajah hai ki parallel buses ek wall se takraati hain. Agar do wires length mein $\delta l$ se differ karti hain, unke arrival times mein fark hoga $\Delta t_{skew}=\frac{\delta l}{v}.$ Figure dekho: do bits saath launch hue, ek wire lambi, toh red bit late pahunchti hai. Agar late bit settle nahi hui jab clock sample kare, toh garbage padha jaata hai. Yahi bilkul wajah hai ki parent $\Delta t_{skew}$ ko $T_{clk}$ se compare karta hai: $28\text{ps}$ skew $7500\text{ps}$ period ke andar theek hai lekin $200\text{ps}$ wale ke andar fatal hai.

7. Setup aur hold — sampling ka "quiet window"

Isliye parent ka clock-limit padhta hai $T_{clk}\ge \Delta t_{skew}+t_{setup}+t_{hold}$: period mein skew plus yeh quiet window fit hona chahiye. Us formula ka har symbol ab define hai.

8. Differential pair — do wires ek hi kahaani sunate hue

Yeh topic iske liye kyun zaroori hai: serial links ek single differential pair pe bhejte hain. Figure mein, noise dono wires pe equally hit karti hai (grey bump dono pe), toh difference mein cancel ho jaati hai — receiver usse sun hi nahi sakta. Isliye parent claim karta hai ki serial "crosstalk ko common-mode noise ki tarah reject karta hai." Common-mode = woh part jo dono wires share karte hain; receiver use ignore karta hai aur sirf opposite (differential) part rakhta hai.

9. Symbols, bits-per-symbol $b$, aur rates

${\log }_2$ kyun aur simple counting nahi? Har extra bit distinguishable levels ki sankhya double kar deta hai ($1$ bit → $2$ levels, $2$ bits → $4$, $3$ bits → $8$). Woh function jo doubling ko undo karta hai — "itne levels tak pahunchne ke liye kitni doublings?" — exactly ${\log }_2$ hai. Isliye parent ka data-rate formula $b$ se multiply karta hai.

Inhe saath rakhke, parent ka serial rate padhta hai $R_{data}=R_s\cdot \eta \cdot b,$ ab har letter ka ek matlab hai: symbols/sec $\times$ useful fraction $\times$ bits/symbol.

10. PLL — ek clock multiplier

Yeh topic iske liye kyun zaroori hai: serializer ko parallel data aane se $8\times$ tezi se bits shift out karne padte hain, toh use ek $8\times$ clock chahiye. PLL $f_{high}=n\cdot f_{low}$ banata hai. Yahi parent ke serializer walk-through mein "Fast Clock Multiplication" step hai.

11. CDR aur phase $\varphi$

Beech mein sample kyun karo? Edges wahan hain jahan voltage ramp kar rahi hai aur uncertain hai; ek bit ka middle woh flat, confident plateau hai. Parent ka rule $|\Delta \varphi |<\frac{T_{bit}}{2}$ bas yeh kehta hai: agar tumhara sampling point middle se aadhe bit se zyada drift ho jaaye, tum neighbouring bit mein gir jaate ho. Yahan $T_{bit}=\frac{1}{R_s}$ ek bit ka time hai — same reciprocal trick jaise $T_{clk}$.

Yeh foundations topic ko kaise feed karte hain

Equipment checklist

Right side cover karo aur zor se jawab do; check karne ke liye reveal karo.