Serial vs parallel signaling (SerDes): Worked examples

6.3.12 · D3 · Hardware › Interconnects, Buses & SoC › Serial vs parallel signaling (SerDes)

Yeh page parent SerDes note ki "number pe laao" companion hai. Parent ne tumhe formulas diye; yahan hum har tarah ke questions dhundte hain jo wo formulas produce kar sakte hain aur har ek ko ek checkable number tak grind karte hain.

Scenario matrix

Har SerDes numeric question in situations mein se ek hoti hai. Columns woh quantity hain jo tum solve karte ho; rows woh regime hain (kaun sa physical effect dominate karta ya degenerate hota hai).

Regime → \ Solves for →	Skew / parallel limit	Serial data rate	Timing / CDR margin
Low speed (skew tiny)	Ex 1	—	—
High speed (skew fatal)	Ex 2	—	—
Degenerate / ideal (zero input)	Ex 3 (zero skew)	—	Ex 7 (zero drift)
Encoding overhead	—	Ex 4 (8b/10b), Ex 5 (128b/130b)	—
Multi-lane scaling	—	Ex 6 (x16)	—
Bit-period / sampling	—	—	Ex 8 (CDR budget)
Real-world word problem	Ex 9 (cable choice)	Ex 9	Ex 9
Exam twist (limiting value)	Ex 10 (crossover speed)	Ex 10	Ex 10

Do constants jo hum har jagah reuse karte hain:

Yeh raha wahi map picture ke roop mein — kaun sa example kis regime mein baithta hai:

Figure — Serial vs parallel signaling (SerDes)

Case: parallel skew regime

Ex 1 — Low speed, skew harmless (matrix: Low speed / skew limit)

Worked example Ek gentle 100 MHz parallel bus

Ek 32-bit parallel bus $100 MHz$ pe chalta hai. Shortest aur longest data trace ke beech worst-case trace-length mismatch $8 mm$ hai. Clock period ka kitna fraction skew se kho jaata hai? Kya bus safe hai?

Forecast: Abhi guess karo — kya skew period ke 1% se neeche hai, ya 10% se upar? (Sirf 100 MHz pe period lamba hai, toh bet lagao "tiny" pe.)

Length mismatch ko time (skew) mein convert karo. $Δ t_{s k e w} = \frac{l}{v} = \frac{8 \times 1 0 ^{- 3}}{1.8 \times 1 0 ^{8}} = 4.44 \times 1 0^{- 11} s = 44.4 ps$ Yeh step kyun? Skew sirf ek delay difference hai; extra $8 mm$ copper hi hai jo ek bit ko late arrive karaata hai. Delay = distance ÷ speed.
Clock period nikalo. $T_{c l k} = \frac{1}{100 \times 1 0 ^{6}} = 10 ns = 10000 ps$ Yeh step kyun? Hum skew ko relative judge karte hain — kitni der ek bit settle ho sakti hai — yaani period se.
Skew ko fraction mein compute karo. $\frac{44.4}{10000} = 0.00444 = 0.44%$ Yeh step kyun? Percentage hi ek honest measure hai: 44 ps meaningless hai jab tak period se compare na ho.

Verify: 0.44% ≪ typical 15% danger threshold → safe. Units: ps/ps dimensionless hai, correct. Sanity: slow clock ⇒ skew negligible, parent ke "at 1 GHz it's still fine" claim se match karta hai.

Ex 2 — High speed, skew fatal (matrix: High speed / skew limit)

Worked example Wahi wires 6 GHz pe

$8 mm$ mismatch rakho (skew $= 44.4 ps$ Ex 1 se). Ab parallel clock ko $6 GHz$ tak push karo. Period ka kitna fraction skew hai, aur yeh serial ki taraf switch karne par kyun majboor karta hai?

Forecast: Period 60× shrink ho gaya. Guess karo: kya skew ab period ke quarter se zyada ho gaya?

Naya period. $T_{c l k} = \frac{1}{6 \times 1 0 ^{9}} = 1.667 \times 1 0^{- 10} s = 166.7 ps$ Yeh step kyun? Higher frequency = shorter period; physical skew nahi badla, sirf budget badla.
Kho gaya fraction. $\frac{44.4}{166.7} = 0.266 = 26.6%$ Yeh step kyun? Wahi skew, tiny period ⇒ skew ab har bit window ka ek quarter se zyada kha jaata hai.

Verify: $26.6% > 15%$ danger line → bus reliably sample nahi kar sakta. Isliye designers ek single differential serial lane ki taraf jaate hain jahan multi-wire alignment khatam ho jaata hai. Sanity: Ex 1 se skew fraction 0.44% tha; frequency ko 60 se multiply karne se fraction bhi 60 se multiply hota hai → $0.44% \times 60 = 26.6%$ . ✓

Ex 3 — Degenerate case: zero skew (matrix: Ideal / skew limit)

Worked example Impossible perfect PCB

Maano ek magical PCB saari traces ko exactly equal length banata hai, toh $Δ t_{s k e w} = 0$ . $t_{se t u p} = 30 ps$ aur $t_{h o l d} = 20 ps$ ke saath, maximum parallel clock frequency kya hai?

Forecast: Zero skew ke saath, kya speed limit infinite hai, ya koi cheez phir bhi cap karti hai?

Period floor yaad karo (parent ke skew formula se): $T_{c l k} \geq Δ t_{s k e w} + t_{se t u p} + t_{h o l d}$ Yeh step kyun? Perfect traces ke saath bhi, flip-flop ko latch karne ke liye setup + hold time chahiye.
Zero skew substitute karo. $T_{c l k} \geq 0 + 30 + 20 = 50 ps$ Yeh step kyun? Yeh woh degenerate input hai jo matrix demand karta hai — yeh dikhata hai ki skew sirf limit nahi hai.
Frequency ke liye invert karo. $f_{ma x} = \frac{1}{50 \times 1 0 ^{- 12}} = 2.0 \times 1 0^{10} Hz = 20 GHz$

Verify: Perfect bus bhi 20 GHz pe cap ho jaata hai setup+hold ki wajah se. Units: $1/ s = Hz$ . ✓ Sanity: skew hatane se limit badhi lekin infinite nahi hui — yahi degenerate-input check ka lesson hai.

Case: serial data-rate regime

Ex 4 — 8b/10b encoding overhead (matrix: Encoding / data rate)

Worked example 3 Gbaud lane ke saath 8b/10b

Ek serial lane symbol rate $R_{s} = 3 Gbaud$ pe transmit karta hai NRZ ( $b = 1$ bit/symbol) aur 8b/10b encoding use karke. Usable data rate kya hai?

Forecast: 8b/10b har 8 data bits ke liye 10 bits bhejta hai. Efficiency aur final Gbps guess karo.

Efficiency nikalo. $η = \frac{k}{n} = \frac{8}{10} = 0.8$ Yeh step kyun? Har 10 transmitted bits mein se 2 koi user data carry nahi karte — woh DC balance aur CDR ke liye clock edges khareed rahe hain.
Data-rate engine apply karo. $R_{d a t a} = R_{s} \cdot η \cdot b = 3 \times 1 0^{9} \times 0.8 \times 1 = 2.4 \times 1 0^{9} bps = 2.4 Gbps$ Yeh step kyun? Symbols/sec × (fraction jo real data hai) × (bits/symbol) = user bits/sec.

Verify: $3 Gbaud \to 2.4 Gbps$ ; tumne encoding ke liye 20% pay kiya. Units: Gbaud×(dimensionless)×(bits/symbol)=Gbps. ✓ Yeh exactly SATA / USB 3.0 style overhead hai.

Ex 5 — Low-overhead 128b/130b (matrix: Encoding / data rate)

Ex 6 — Multi-lane scaling (matrix: Multi-lane / data rate)

Case: timing & CDR regime

Ex 7 — Degenerate case: zero frequency drift (matrix: Ideal / CDR)

Worked example Perfectly matched crystals

Transmitter aur receiver bilkul same reference frequency share karte hain, toh sampling clock kabhi drift nahi karta. Ideal signaling ke saath, CDR ko kitna phase error correct karna hai, aur kya link ko phir bhi CDR ki zaroorat hai?

Forecast: Zero drift — kya CDR ab useless hai?

Frequency offset zero hai, toh drift se accumulated timing error $0 ps$ hai. Yeh step kyun? Drift error (frequency difference)×(time) ke roop mein badhta hai; zero difference ke saath, yeh flat zero hai.
Lekin phir bhi koi separate clock wire nahi hai. Receiver ko start-up pe ek baar mid-bit dhundna hai. Yeh step kyun? Yeh degenerate case dikhata hai ki CDR ka kaam do parts mein hai: (a) drift track karna — ab $0$ , aur (b) initial sampling phase dhundna — abhi bhi required.

Verify: $0$ drift ke saath bhi, CDR phase acquire karne ke liye still needed hai; sirf tracking load zero ho jaata hai. Ex 8 se sanity check: wahan drift budget wahi hai jo yahan kuch nahi reh jaata.

Ex 8 — CDR sampling budget (matrix: Bit-period / CDR)

Worked example USB 3.0 half-bit rule

USB 3.0 $5 Gbps$ pe chalta hai (NRZ, toh 1 symbol = 1 bit). Bit period aur maximum allowed CDR phase error compute karo.

Forecast: Rule hai "half a bit ke andar sample karo". $T_{bi t}$ aur half-bit window ps mein guess karo.

Bit period. $T_{bi t} = \frac{1}{R _{s}} = \frac{1}{5 \times 1 0 ^{9}} = 2.0 \times 1 0^{- 10} s = 200 ps$ Yeh step kyun? Bit rate aur bit period reciprocals hain; yeh poora timing budget set karta hai.
Half-bit rule apply karo (parent ke CDR formula se): $∣Δ ϕ ∣ < \frac{T _{bi t}}{2} = \frac{200}{2} = 100 ps$ Yeh step kyun? Mid-bit se half se zyada der se sample karo toh tum agale bit mein land karte ho — guaranteed error.

Verify: 100 ps window parent ke stated USB 3.0 budget se match karta hai. ✓ Unka measured $Δ ϕ \approx \pm 10 ps$ 100 ps ke andar comfortably baithta hai. Units: $1/ (bits/s) = s/bit$ . ✓

Ex 9 — Real-world word problem (matrix: word problem, spans all columns)

Worked example "Cable ya PCB?" engineering decision

Tumhe do chips ke beech $12 cm$ ki doori par $10 Gbps$ user data move karna hai. Option A: ek 16-bit parallel bus. Option B: ek single serial lane $12.5 Gbaud$ NRZ pe 8b/10b ke saath. (a) Kya Option B 10 Gbps requirement meet karta hai? (b) Option A ke liye, $6 mm$ mismatch se per-wire skew kya hoga, aur 16 wires ko kaun sa clock chahiye?

Forecast: Serial ke jeetne par bet lagao; guess karo parallel clock comfortable ya scary range mein padta hai.

Serial usable rate (Option B). $R_{d a t a} = 12.5 \times 1 0^{9} \times 0.8 \times 1 = 10.0 \times 1 0^{9} = 10.0 Gbps$ Yeh step kyun? Requirement ko directly data-rate engine se check karo; 8b/10b ⇒ $η = 0.8$ .
Serial verdict: $10.0 Gbps =$ requirement → ek differential pair pe exactly meet karta hai.
Parallel skew (Option A). $Δ t_{s k e w} = \frac{6 \times 1 0 ^{- 3}}{1.8 \times 1 0 ^{8}} = 3.33 \times 1 0^{- 11} = 33.3 ps$ Yeh step kyun? Parallel ka dushman skew hai; mismatch ko time mein convert karo.
Parallel clock needed. 16 wires total 10 Gbps carry karne ke liye $10/16 = 0.625 Gbps per wire$ chahiye, yaani $625 MHz$ , period $1600 ps$ . Skew fraction: $\frac{33.3}{1600} = 2.08%$ Yeh step kyun? Hume confirm karna hai ki required clock pe skew tolerable hai.

Verify: Serial 10.0 Gbps 2 wires pe hit karta hai; parallel 16 wires pe 2.08% skew ke saath hit karta hai — technically theek hai lekin 8× pin count aur EMI ke saath. Serial choose karo (Option B). Units sab consistent hain (ps/ps, Gbps). ✓

Ex 10 — Exam twist: the crossover speed (limiting value) (matrix: limiting value)

Worked example Parallel "kab marega"?

Parallel ko unusable define karo jab skew clock period ke $25%$ tak pahunch jaaye. Fixed skew $Δ t_{s k e w} = 40 ps$ wale bus ke liye, woh clock frequency nikalo jahan parallel marega (limiting value).

Forecast: Woh period solve karo jahan $40 ps$ exactly ek quarter ho, phir invert karo. GHz guess karo.

Limiting condition set karo. $\frac{Δ t _{s k e w}}{T _{c l k}} = 0.25 \Rightarrow T_{c l k} = \frac{Δ t _{s k e w}}{0.25} = \frac{40}{0.25} = 160 ps$ Yeh step kyun? "25% pe marega" ek equation hai; isse solve karne par exact period boundary milti hai — woh limiting value jo matrix chahta hai.
Frequency ke liye invert karo. $f_{d i e} = \frac{1}{160 \times 1 0 ^{- 12}} = 6.25 \times 1 0^{9} Hz = 6.25 GHz$ Yeh step kyun? 6.25 GHz se neeche parallel theek hai; usse upar, yeh bus dead hai — serial ki taraf crossover.

Verify: $6.25 GHz$ se neeche → skew < 25% → OK; usse upar → parallel unusable. Ex 2 se cross-check: 6 GHz pe 44.4 ps wala bus 26.6% pe tha (already dead), consistent hai kyunki uska skew 40 ps se zyada hai. ✓ Units: $1/ s = Hz$ . ✓

Recall Self-test — answers cover karo

USB 3.0 at 5 Gbps: bit period? ::: $200 ps$ , toh CDR window $= 100 ps$ . 8b/10b efficiency aur uska cost? ::: $η = 0.8$ ; tum DC balance + edges ke liye 20% overhead pay karte ho. PCIe Gen3 per-lane rate? ::: $8.0 \times \frac{128}{130} = 7.877 Gbps$ . Zero skew parallel speed infinite kyun nahi deta (Ex 3)? ::: setup + hold phir bhi period ko floor karta hai (yahan 50 ps → 20 GHz). 25% rule pe 40 ps-skew bus ke liye crossover speed? ::: $6.25 GHz$ .

Yeh bhi dekho: Equalization (CTLE, DFE) aur PLL and Clock Synthesis — kaise real receivers un sampling windows ko widen karte hain jo inhi examples ne assume kiye, aur DDR Memory Interface — woh modern parallel bus jo per-bit training se skew se ladhta hai.