Serial vs parallel signaling (SerDes): Question bank

6.3.12 · D5 · Hardware › Interconnects, Buses & SoC › Serial vs parallel signaling (SerDes)

Pehle yeh vocabulary padho

Quiz se pehle inhe padh lo — neeche kaafi traps inhe precisely jaanne par depend karte hain.

True ya false — justify karo

Neeche har claim ya toh true hai ya false. Pehle "true" ya "false" bolo, phir reason do.

Serial links faster hote hain parallel se kyunki electrons ek single wire par faster move karte hain.

False — electrons faster nahi move karte. Serial isliye jeetta hai kyunki ek lane ko cross-wire skew alignment ki zaroorat nahi, isliye uska clock parallel bus se kaafi zyada high run kar sakta hai jo apne worst-aligned pair se limited hoti hai.

8 GT/s par 1-lane serial link hamesha 133 MHz par 64-bit parallel bus se raw throughput mein beat karta hai.

False — 64 × 133 MHz ≈ 8.5 Gbps parallel payload roughly ek 8 GT/s lane (≈ 7.9 Gbps) ke barabar hai, toh ek single lane sirf comparable hai; serial jeetta hai bahut saari independent lanes add karke bina skew penalty ke.

Differential signaling crosstalk ko poori tarah remove kar deta hai.

False — yeh zyaatar external noise ko common-mode noise mein convert karta hai jise receiver subtract kar leta hai, lekin pairs ke beech coupling aur imperfect balance abhi bhi residual crosstalk chhodti hai.

Serial link ko data pair ke saath ek dedicated clock wire chahiye hoti hai.

False — yeh exactly wahi cheez hai jo serial avoid karta hai; clock data edges mein embedded hoti hai aur clock-data recovery (CDR) se rebuild hoti hai, isliye data patterns mein frequent transitions guarantee karne zaroori hain.

8b/10b encoding link ko faster banata hai.

False — yeh raw bit ke per slower banata hai (sirf

η = 0.8

payload: 10 transmitted mein se 8 useful bits), lekin yeh transition density aur DC balance guarantee karta hai taaki CDR lock kar sake aur receiver sahi biased rahe. Dekho 8b/10b Encoding.

Wider parallel buses hamesha narrower ones se zyada bandwidth dete hain.

False — ek point ke baad, wires badhane se skew spread, crosstalk, aur pin count badhta hai, jo shared clock ko slow karne par majboor karta hai; net bandwidth gir sakti hai, isliye industry serial ki taraf gayi.

PAM-4 same symbol rate par data rate free mein double kar deta hai.

False — yeh 2 bits per symbol pack karta hai, lekin chaar voltage levels ek doosre ke paas hote hain, isliye eye chhota hota hai aur zyada strong equalization aur lower noise demand karta hai. Dekho Eye Diagrams aur Equalization (CTLE, DFE).

Closed eye diagram ka matlab hai physical wire toot gayi hai.

False — closed eye ka matlab hai bit periods itne bure tarike se overlap kar rahe hain (skew, ISI, jitter, ya noise se) ki sampler koi clean point nahi dhundh sakta; wire theek ho sakti hai lekin under-equalized ho. Dekho Eye Diagrams.

Transmitter aur receiver ko serial link kaam karne ke liye exact same crystal frequency share karni chahiye.

False — yeh independent crystals par run karte hain thodi si frequency differences ke saath; CDR continuously incoming edge rate track karta hai taaki receiver ka sampling clock transmitter ka follow kare, drift absorb karte hue.

Data wires ke beech skew ek single serial lane par bhi problem hai, bas chhoti.

False — single lane mein sirf ek differential pair hota hai, isliye inter-wire data skew hota hi nahi; skew tabhi wapas aata hai jab aapko multiple lanes align karne padte hain (jaise PCIe x16 lane-to-lane deskew). Dekho PCIe Protocol.

Galti dhundho

Har statement mein ek galat word ya claim hai. Use naam do aur theek karo.

"Setup time yeh hai ki clock edge ke baad kitni der tak data stable rehna chahiye."

Galat — yeh hold time describe kar raha hai; setup time woh hai kitni der pehle edge se data already stable hona chahiye.

"Higher clock rates par, ek fixed 28 ps skew clock period ka ek chhota fraction ban jaata hai."

Galat — higher rate ka matlab chhota period hota hai, isliye wahi 28 ps ek bada fraction ban jaata hai; yahi exactly reason hai kyun parallel buses stall ho jaati hain.

"CDR maximum accuracy ke liye signal edges par hi data sample karta hai."

Galat — yeh mid-bit par sample karta hai, edges se jitna ho sake door, kyunki edges par hi transitions aur jitter rehte hain; eye beech mein sabse wide hoti hai.

"Crosstalk sirf trace length par depend karta hai, data pattern par nahi."

Galat — crosstalk aggressor ke

\frac{d V}{d t}

ke proportional hota hai, isliye 0101 jaisa fast-switching pattern static wale se kaafi zyada inject karta hai; yeh data-dependent hai.

"Ek serializer apna shift register parallel input ke same clock par run karta hai."

Galat — yeh clock multiply karta hai: ek

n : 1

serializer

n \times f_{l o w}

par shift karta hai ek PLL use karke, toh 8 bits us time mein nikalte hain jitne mein ek parallel word aata hai. Dekho PLL and Clock Synthesis.

"PCIe Gen3 ka 128b/130b encoding 8b/10b ki tarah 20% bandwidth waste karta hai."

Galat — 128b/130b overhead sirf

2/130 \approx 1.5%

hai (

η \approx 0.985

); 8b/10b 20% waste karta hai. Newer generations ne coding overhead scrambling se trade kiya. Dekho PCIe Protocol.

"Parallel bus se EMI is baat se independent hai ki kitni lines ek saath switch karti hain."

Galat — radiated power simultaneously switching traces ki number ke saath scale karta hai (

P \propto n

), isliye bahut saare aligned edges ek differential pair se kaafi zyada radiate karte hain jiske currents cancel ho jaate hain.

"Equalization signal energy add karta hai taaki link faster jaye."

Galat — equalization energy add nahi karta; yeh frequency response ko reshape karta hai (un high frequencies ko boost karta hai jo channel ne attenuate ki thi) taaki eye reopen ho. Dekho Equalization (CTLE, DFE).

Why questions

Sirf outcome nahi, mechanism ke saath jawab do.

Serial link ko data mein frequent bit transitions ki zaroorat kyun hoti hai?

Kyunki receiver ka CDR apna clock data edges se extract karta hai; identical bits ki lambi run se koi edges nahi milti, isliye recovered clock drift karta hai aur sampling lock kho deti hai — isliye line coding transitions force karta hai.

Differential signaling single-ended ke comparison mein EMI kyun reduce karta hai?

Dono wires equal-and-opposite currents carry karte hain, isliye unke radiated fields far field mein largely cancel ho jaate hain, trace pair ke antenna effect ko dramatically lower karte hain. Dekho Differential Signaling.

DDR memory parallel rahi jabki PCIe serial ho gayi — kyun?

DDR ko bahut low latency chahiye aur short, matched, tightly-controlled traces chahiye jahan skew manageable ho aur point-to-point distance chhota ho; serialization overhead (SerDes latency, encoding) memory ke latency-critical access ko hurt karta. Dekho DDR Memory Interface.

Sampling clock phase error half a bit period se kam kyun rehna chahiye?

Agar phase error

\frac{T _{bi t}}{2}

(ek bit slot

T_{bi t} = \frac{1}{R _{s}}

ka aadha) se zyada ho jaaye, toh sampling instant aglay bit ke window mein chali jaati hai, isliye receiver galat symbol latch karta hai — CDR feedback loop usi error ko near zero rakhne ke liye exist karta hai.

Crosstalk faster signal edges ke saath kyun bura ho jaata hai?

Coupling

\frac{d V}{d t}

ke proportional hota hai; sharper edge ka matlab voltage change ki larger rate, jo neighbouring victim trace par bada current aur voltage induce karti hai.

Parallel bus ko serial se beat karne ke liye bas zyada wide kyun nahi karte?

Zyada wires skew spread, crosstalk victims, EMI sources, aur package pins ek saath multiply karte hain, jo shared clock ko neeche force karta hai — aggregate cost aur skew ceiling bandwidth benefit se faster grow karte hain.

Longer channel hone par eye diagram kyun narrow ho jaata hai?

Longer channels high-frequency content ko zyada attenuate aur delay karte hain, har symbol ko uske neighbours mein spread karte hain (inter-symbol interference), jo vertical aur horizontal eye opening collapse kar deta hai. Dekho Eye Diagrams.

Edge cases

Boundary aur degenerate scenarios jo topic quietly assume karke chal deta hai.

Ek serial link par agar data hamesha ke liye constant 1s ka stream ho toh kya hoga?

Koi transitions nahi honge toh CDR edges ke liye starve karega aur drift karega; isliye encoders (8b/10b, scrambling) maximum run length guarantee karte hain taaki koi pathological all-ones payload wire par kabhi appear na ho sake.

Agar do parallel traces ki zero length mismatch ho, toh kya skew zero hoga?

Zaroor nahi — skew alag driver strengths, PCB layer permittivity, via count, aur loading se bhi aata hai; equal length sirf propagation-delay component remove karta hai.

Bahut low clock rate par, kya parallel bus serial se better hai?

Aksar haan — jab period skew se kaafi bada ho aur crosstalk negligible ho, parallel simple, low-latency, no-encoding logic ke saath high throughput deta hai; yahi exactly woh regime hai jahan legacy parallel buses rehti thi.

Long idle period mein jab koi traffic na ho toh CDR kya kar raha hota hai?

Koi edges nahi milti toh yeh apna last locked phase/frequency open-loop hold karta hai aur slowly drift karta hai; links isliye idle/training sequences bhejte hain taaki CDR edges dekhta rahe aur locked rahe.

Agar skew exactly setup-plus-hold budget ke barabar ho aur data-valid time zero ho, toh kya hoga?

Valid window collapse hokar kuch nahi bachta — koi ek instant nahi hai jab saari bits full setup+hold ke liye simultaneously stable hon, isliye receiver reliably sample nahi kar sakta; bus apni hard frequency ceiling hit kar chuki hai.

Kya ek single serial lane mein lane-to-lane skew ho sakta hai?

Nahi — "lane-to-lane" skew ek lane ke liye undefined hai; yeh sirf multi-lane links (jaise PCIe x8/x16) mein appear karta hai jahan independent CDRs thodi alag phases recover karte hain aur ek deskew buffer unhe realign karta hai. Dekho PCIe Protocol.

Recall Quick self-test

Teen physics problems kaun se hain jinne high-speed parallel buses ko khatam kiya. ::: Wires mein skew accumulation, traces ke beech data-dependent crosstalk, aur bahut saari simultaneously switching lines se EMI. Woh ek mechanism kaun sa hai jo serial receiver ko clock wire ke bina kaam karne deta hai? ::: Clock-data recovery (CDR), jo sampling clock ko data ki apni edges se rebuild karta hai. 8b/10b ka 20% overhead pay karna worth kyun hai? ::: Yeh transition density aur DC balance guarantee karta hai taaki CDR locked rahe aur receiver biased rahe — reliability bandwidth ke cost par kharidi gayi hai. GT/s aur Gbps mein kya fark hai? ::: GT/s wire par symbol (transfer) rate hai; Gbps encoding overhead subtract karne ke baad useful payload bit rate hai — GT/s ≥ Gbps.