Interconnects, Buses & SoC

Question 1

(a) Gen4 per-lane raw = 16 GT/s. Encoding efficiency 128b/130b. Useful bits/s = $16 \times 10^9 \times \frac{128}{130} = 15.754 \times 10^9$ bits/s. (2 — rate × encoding) Bytes: $\div 8 = 1.969 \times 10^9$ B/s $\approx 1.97$ GB/s per lane per direction. (2 — byte conversion)

(b) Requirement 48 GB/s.

• Gen4: lanes $= 48 / 1.969 = 24.4 \Rightarrow$ round up to next power-of-two width $\Rightarrow$ x32 — not a standard width, so Gen4 cannot meet 48 GB/s (max x16 ≈ 31.5 GB/s). (2)
• Gen5 per-lane $= 2 \times 1.969 = 3.938$ GB/s. Lanes $= 48/3.938 = 12.2 \Rightarrow$ x16. (2)

(c) At x8:

• Gen5 x8 $= 8 \times 3.938 = 31.5$ GB/s — fails (< 48). (2)
• No PCIe generation in the table meets 48 GB/s at x8 (Gen5 x8 is the highest = 31.5). So none meet the requirement at x8. (2 — must state none, with number)

Question 2

(a) With fixed priority and continuous M0 requests, M0 wins every arbitration slot; M1–M3 never get the bus $\Rightarrow$ starvation. Even if M0 is bursty, if M0's request rate keeps the bus busy, lower masters wait indefinitely. (3)

(b) Hybrid scheme (5):

• Reserve M0 at highest fixed priority but cap it: M0 may win at most 1 grant, then is forced to yield for 2 slots (a "credit"/leaky-bucket limiter) so it cannot monopolize. (2)
• Among M1–M3 use round-robin for the remaining slots, guaranteeing each eventually gets the bus. (2)
• M0's 3-slot bound: since M0 is highest priority whenever it requests and is never delayed more than the slots it deliberately yields, its next request is served within ≤3 slots. (1)

(c) Worst case for M3: In every window of slots, M0 may take 1 slot per its allowed period, then M1, M2 each get a round-robin turn before M3. Worst-case wait between two M3 grants:

• Between M3's grants, M0 can insert grants (bounded), plus M1 and M2 each get one round-robin turn.
• Round-robin among M1–M3 gives M3 one slot per 3 best-effort slots; interleaved with M0 grants (≤1 per M0-period), worst case ≈ 5 slots (M0, M1, M0, M2, then M3). Accept 4–5 with justification. (4)

Question 3

(a) Max burst = 256 beats × 16 B = 4096 bytes. (2) Peak throughput = 16 B × 1 GHz = $16 \times 10^9$ B/s = 16 GB/s (128 bit × 1 GHz). (2)

(b) With multiple outstanding IDs, the master can issue new read addresses on the AR channel without waiting for prior read data on the R channel; the interconnect/memory pipelines them, so latency of request N overlaps with data transfer of earlier requests. (2) One 256-beat burst transfers in 256 cycles = 256 ns (at 1 GHz). To hide 200 ns latency you need enough in-flight data to cover the gap while waiting: latency/burst-time $= 200/256 = 0.78 \Rightarrow$ 1 outstanding burst already covers 200 ns since one burst's transfer time (256 ns) ≥ 200 ns latency. So ≥1 additional outstanding burst (i.e. 2 in flight) fully hides it. Accept answer of 2 outstanding (1 transferring + 1 queued). (3 — arithmetic + reasoning)

(c) AXI mandates data ordering within a single ID because the master associates returned beats with the request order for that ID; there is no per-beat tag, so out-of-order within an ID would be ambiguous. Different IDs carry independent order info and may interleave/reorder. (3)

Question 4

(a) (4, 2 each)

• Bandwidth: NVLink provides far higher aggregate GPU-GPU bandwidth (hundreds of GB/s to ~TB/s per GPU) vs PCIe Gen5 x16 ≈ 63 GB/s bidirectional; all-reduce is bandwidth-bound.
• Topology: NVLink allows direct mesh/switched (NVSwitch) GPU-to-GPU links avoiding host/CPU bottleneck and PCIe root-complex serialization; PCIe funnels peer traffic through the root complex or PCIe switch with lower bisection.

(b) CXL.mem exposes the device memory as cache-coherent, load/store addressable host memory, so the CPU accesses it with normal memory semantics and coherence—unlike PCIe which is a non-coherent, packetized I/O protocol requiring explicit DMA. CXL runs on the PCIe PHY but adds coherence/memory protocols on top, enabling memory pooling/expansion. (4)

(c) (4, 2 each)

• Electrical: A shared parallel bus's capacitive load and skew grow with each drop; high-speed signaling on many parallel wires across 8 devices is not feasible (reflections, clock skew) — bandwidth per device drops as it's shared/multiplexed.
• Protocol: A shared bus serializes all traffic (one transfer at a time), so aggregate bandwidth does not scale with node count; all-reduce needs concurrent point-to-point links. Alternative on-package: mesh/fabric interconnect (e.g., Infinity Fabric / NoC mesh) or NVSwitch crossbar.

Question 5

(a) Parallel: 32 wires × 200 Mb/s/wire = $32 \times 0.2 = 6.4$ Gb/s. (2) SerDes: 1 pair × 8 Gb/s = 8 Gb/s. SerDes delivers more (8 > 6.4 Gb/s). (2)

(b) (4, 2 each) Any two:

• Fewer wires/pins → lower package cost, easier PCB routing.
• No inter-wire skew problem (parallel buses limited by skew at high speed); embedded clock in serial stream.
• Differential signaling → better noise immunity, longer reach.

(c) 4×4 mesh: diameter = $(4-1) + (4-1) = 6$ hops (corner to corner). (2) Scalability: a shared bus offers fixed aggregate bandwidth shared among all nodes (drops per node as N grows), while a mesh provides multiple concurrent paths—bisection bandwidth scales, so aggregate throughput grows with node count. (2)

[
  {"claim":"Gen4 per-lane usable ~1.97 GB/s","code":"rate=16e9; enc=128/130; Bps=rate*enc/8; result = abs(Bps-1.969e9) < 5e6"},
  {"claim":"Gen5 x16 usable ~63 GB/s meets 48","code":"per_lane=32e9*128/130/8; total=per_lane*16; result = total/1e9 > 48"},
  {"claim":"Gen5 x8 = 31.5 GB/s fails 48","code":"per_lane=32e9*128/130/8; total=per_lane*8; result = total/1e9 < 48"},
  {"claim":"AXI max burst 4096 bytes","code":"result = 256*16 == 4096"},
  {"claim":"AXI 128b@1GHz peak 16 GB/s","code":"result = (16*1e9)/1e9 == 16"},
  {"claim":"Parallel 6.4 < SerDes 8 Gb/s","code":"par=32*0.2; ser=8; result = ser > par"},
  {"claim":"4x4 mesh diameter 6","code":"result = (4-1)+(4-1) == 6"}
]