Interconnects, Buses & SoC

Q1. (4 marks)

• Bus arbitration = the mechanism that decides which master gets control of a shared bus when multiple masters request it simultaneously, preventing conflicts. (2)
• Centralized: a single bus arbiter grants access — e.g. daisy-chaining / centralized parallel priority. (1)
• Distributed: arbitration logic is spread across devices, each decides locally — e.g. self-selection / collision-detection (CSMA). (1)

Q2. (5 marks) — 1 mark per correct rate, encoding half-marks rounded up.

Rates: 3× (2), encodings: correct (3). (PCIe 1.0/2.0 used 8b/10b; 3.0 onward use 128b/130b.)

Q3. (6 marks) (a) Encoding efficiency $= 128/130 \approx 0.9846$. Raw = $16$ GT/s $= 16\times10^9$ bits/s. Usable bits/s $= 16\times 10^9 \times \frac{128}{130} = 15.754\times10^9$ bits/s. (2) Convert to bytes: $\div 8 = 1.969$ GB/s per lane. (2) (b) $\times 8$ link, one direction $= 8 \times 1.969 = 15.75$ GB/s; bidirectional $= 2 \times 15.75 \approx 31.5$ GB/s. (2)

Q4. (4 marks)

• SerDes = Serializer/Deserializer: a block that converts parallel data to a serial stream for transmission and back to parallel at the receiver. (2)
• Reasons (any two, 1 each): fewer wires/pins → cheaper, less board area; avoids clock/data skew between parallel wires at high frequency; less crosstalk; embedded clock allows much higher per-line data rates. (2)

Q5. (5 marks) — 1 mark each channel.

1. AW (Write Address) — write
2. W (Write Data) — write
3. B (Write Response) — write
4. AR (Read Address) — read
5. R (Read Data + response) — read

Q6. (5 marks)

• A DMA controller transfers data directly between memory and I/O (or memory-to-memory) without CPU involvement for each word. (2)
• Benefit: the CPU is freed to do other work instead of moving every byte, and transfers occur at bus speed → higher throughput, lower CPU overhead. (2)
• Cycle-stealing: DMA takes control of the bus for one (or a few) bus cycle(s) at a time, "stealing" cycles between CPU accesses, rather than holding the bus for the whole block (burst mode). (1)

Q7. (5 marks)

• CXL = an open, cache-coherent interconnect built on the PCIe physical layer, enabling low-latency memory and cache sharing between CPU and accelerators/memory devices. (2)
• Three protocols: CXL.io, CXL.cache, CXL.mem. (2)
• CXL 2.0 builds on PCIe 5.0 (32 GT/s). (1)

Q8. (6 marks) (a) Ring: each node connects to exactly two neighbours forming a closed loop; data hops around the ring. Links for $N$ nodes $= N$. (3) (b) 2D Mesh: nodes arranged in a grid, each connected to N/S/E/W neighbours (interior nodes have 4 links). (2) (c) Advantage: multiple concurrent transfers on different links → higher aggregate bandwidth and scalability (bus is shared/serialized). (1)

Q9. (5 marks) (a) IP core = a pre-designed, reusable block of logic/functionality (e.g. a CPU, USB controller) licensed and integrated into an SoC. (2) (b)

• Soft IP: delivered as synthesizable RTL/HDL; portable across processes, flexible, less optimized. (1.5)
• Hard IP: delivered as a fixed placed-and-routed layout (GDSII) for a specific process; optimized for area/speed/power but not portable. (1.5)

Q10. (5 marks) (a) Per link per direction $= 25$ GB/s. Bidirectional per link $= 50$ GB/s. Total $= 12 \times 50 = 600$ GB/s. (3) (b) Advantage (any one): much higher bandwidth than PCIe; cache-coherent/direct GPU-to-GPU memory access; lower latency; dedicated links avoid PCIe root-complex bottleneck. (2)

[
  {"claim":"PCIe 4.0 usable per-lane bandwidth ≈ 1.969 GB/s","code":"rate=16e9; usable=rate*128/130/8; result = abs(usable/1e9 - 1.969) < 0.01"},
  {"claim":"PCIe 4.0 x8 bidirectional ≈ 31.5 GB/s","code":"perlane=16e9*128/130/8; bidir=8*perlane*2; result = abs(bidir/1e9 - 31.5) < 0.1"},
  {"claim":"A100 NVLink3 total bidirectional = 600 GB/s","code":"total=12*25*2; result = total == 600"},
  {"claim":"Ring topology link count for N nodes equals N","code":"N=symbols('N'); links=N; result = simplify(links - N) == 0"}
]