Level 1 — RecognitionInterconnects, Buses & SoC

Interconnects, Buses & SoC

⏱ 20 minutes40 marksprintable — key stays hidden on paper

Level: 1 (Recognition) Time Limit: 20 minutes Total Marks: 40

Section A — Multiple Choice (1 mark each, 10 marks)

Select the single best answer.

Q1. In a PCIe link, "x8" refers to:

(a) 8 GB/s of bandwidth
(b) 8 physical lanes, each a differential SerDes pair per direction
(c) 8 devices sharing one bus
(d) A generation-8 encoding scheme

Q2. Which encoding scheme is used by PCIe Gen 3 and Gen 4?

(a) 8b/10b
(b) 128b/130b
(c) NRZ raw with no encoding
(d) PAM4

Q3. The primary purpose of a DMA controller is to:

(a) Increase CPU clock speed
(b) Transfer data between memory and peripherals without CPU intervention per byte
(c) Encrypt bus traffic
(d) Arbitrate PCIe lane assignments

Q4. CXL is built on top of which physical/electrical layer?

(a) NVLink
(b) PCIe
(c) AXI
(d) Ethernet

Q5. Which AMBA/AXI feature allows multiple outstanding transactions to complete out of program order?

(a) Burst-only addressing
(b) Transaction IDs (ID tags)
(c) Single shared clock edge
(d) Tri-state buses

Q6. A mesh Network-on-Chip topology connecting an $N \times N$ grid of routers has a worst-case (maximum) hop count of:

(a) $1$
(b) $2(N-1)$
(c) $N^2$
(d) $\log_2 N$

Q7. NVLink is primarily designed to:

(a) Connect CPU to system DRAM
(b) Provide high-bandwidth, low-latency GPU-to-GPU (and CPU-GPU) interconnect
(c) Replace the SATA storage interface
(d) Serve as an on-chip AXI bridge

Q8. The main motivation for serial signaling (SerDes) over wide parallel buses at high speeds is:

(a) Serial is always cheaper in silicon area
(b) Avoiding inter-lane skew and reducing pin/trace count at high frequencies
(c) Serial links require no clocking
(d) Parallel buses cannot carry differential signals

Q9. In centralized bus arbitration, the component that decides which master gets the bus is the:

(a) Bridge
(b) Arbiter
(c) Decoder
(d) Transceiver

Q10. Among the three CXL protocols, which one provides cache-coherent access for an accelerator to host memory?

(a) CXL.io
(b) CXL.cache
(c) CXL.mem (used alone for host caching)
(d) CXL.serial

Section B — Matching (1 mark each, 10 marks)

Match each term (Q11–Q20) to its best description (A–J). Each used once.

#	Term		Description
Q11	AXI	A	AMD's coherent die-to-die and package interconnect fabric
Q12	Infinity Fabric	B	On-chip packet-switched network of routers replacing shared buses
Q13	SerDes	C	Reusable pre-designed hardware block integrated into an SoC
Q14	NoC	D	AMBA high-performance protocol with separate read/write channels
Q15	IP core	E	Serializer/deserializer converting parallel data to a serial stream
Q16	PCIe root complex	F	Connects the CPU/host to the PCIe device hierarchy
Q17	Arbitration	G	Mechanism deciding which master controls a shared bus
Q18	DMA descriptor	H	Structure specifying source, destination, and length for a transfer
Q19	CXL.mem	I	Protocol letting the host access device-attached memory
Q20	Torus topology	J	Ring-based NoC with wraparound links reducing hop count vs mesh

Section C — True/False WITH Justification (2 marks each: 1 verdict + 1 justification, 20 marks)

State True or False and give a one-line justification.

Q21. PCIe is a shared parallel bus where all devices contend for the same wires. (2)

Q22. Doubling the number of PCIe lanes (same generation) roughly doubles the link bandwidth. (2)

Q23. PCIe Gen 5 per-lane raw bit rate is 32 GT/s, double that of Gen 4. (2)

Q24. A daisy-chain / ring bus topology generally offers lower average latency between arbitrary nodes than a full crossbar. (2)

Q25. AXI uses five independent channels: read address, read data, write address, write data, and write response. (2)

Q26. DMA transfers require the CPU to copy each word between the peripheral and memory. (2)

Q27. CXL and NVLink both aim to provide coherent memory sharing between processing elements. (2)

Q28. In an SoC, a single unified clock always drives every IP core at the same frequency. (2)

Q29. For PCIe Gen 3 using 128b/130b encoding, the encoding overhead is under 2%. (2)

Q30. A mesh NoC scales its bisection bandwidth better than a single shared bus as core count grows. (2)

End of paper.

Answer keyMark scheme & solutions

Section A (1 mark each)

Q1 — (b). "xN" denotes N lanes; each lane is an independent differential SerDes pair per direction. Bandwidth and generation are separate concepts.

Q2 — (b). Gen 3 and Gen 4 both use 128b/130b encoding (Gen 1/2 used 8b/10b). PAM4 appears in Gen 6.

Q3 — (b). A DMA controller moves blocks between memory and peripherals autonomously, freeing the CPU from per-byte copies.

Q4 — (b). CXL runs over the PCIe physical layer (PCIe 5.0/6.0 PHY), reusing its electricals.

Q5 — (b). AXI transaction ID tags allow outstanding transactions and out-of-order completion.

Q6 — (b). Manhattan distance across an $N\times N$ grid: max = $(N-1)+(N-1)=2(N-1)$ .

Q7 — (b). NVLink is a high-bandwidth low-latency GPU-GPU / CPU-GPU interconnect.

Q8 — (b). At high speeds, parallel skew and pin count dominate; serial differential links avoid inter-lane skew and reduce pins.

Q9 — (b). The arbiter grants the bus to one master at a time.

Q10 — (b). CXL.cache provides device-side coherent caching of host memory.

Section B (1 mark each)

Q	Ans	Q	Ans
Q11	D	Q16	F
Q12	A	Q17	G
Q13	E	Q18	H
Q14	B	Q19	I
Q15	C	Q20	J

Section C (1 verdict + 1 justification)

Q21 — False. PCIe is a point-to-point, serial, switched interconnect, not a shared parallel bus.

Q22 — True. Bandwidth scales roughly linearly with lane count (aggregate = per-lane rate × lanes), so x8→x16 ≈ doubles it.

Q23 — True. Gen 4 = 16 GT/s per lane; Gen 5 = 32 GT/s per lane, a 2× increase.

Q24 — False. A crossbar gives direct 1-hop paths; ring/daisy-chain latency grows with node count, so it is generally higher, not lower.

Q25 — True. AXI has AR, R, AW, W, and B — five independent channels.

Q26 — False. The point of DMA is that the controller moves data autonomously; the CPU only sets up the transfer and handles the completion interrupt.

Q27 — True. Both provide coherent load/store memory sharing across processing elements (CXL.cache/.mem; NVLink coherence).

Q28 — False. SoCs typically use multiple clock domains; different IP cores run at different frequencies with clock-domain-crossing logic.

Q29 — True. Overhead = $2/130 \approx 1.54\%$ , which is under 2%.

Q30 — True. A shared bus has fixed bisection bandwidth (one transaction at a time), while a mesh's bisection bandwidth grows with grid width, scaling better.

Marking notes

T/F: 1 mark verdict, 1 mark justification. No justification mark if verdict wrong.

[
  {"claim": "Q6: max hop count in NxN mesh is 2(N-1); for N=4 equals 6", "code": "N=4; result = (2*(N-1)==6)"},
  {"claim": "Q29: 128b/130b overhead 2/130 is under 2%", "code": "ov = Rational(2,130); result = (ov < Rational(2,100))"},
  {"claim": "Q22: x16 aggregate is double x8 at same per-lane rate", "code": "rate=16; result = (rate*16 == 2*(rate*8))"},
  {"claim": "Q23: Gen5 32 GT/s is double Gen4 16 GT/s", "code": "result = (32 == 2*16)"}
]