Serial vs parallel signaling (SerDes) — Hinglish notes

6.3.12 · Hardware › Interconnects, Buses & SoC

Parallel aur Serial Signaling kya hote hain?

Humne Parallel se Serial ki taraf shift kyun kiya?

Parallel ka Bottleneck

1980s-90s mein, parallel buses dominant the (ISA, PCI, SCSI). Lekin jaise clock speeds badhi, teen physics problems saamne aayi:

1. Skew Accumulation

Jab tum 8 traces par ek saath 8 bits bhejte ho, trace length, PCB layer, ya driver strength mein chhote farq ki wajah se bits alag-alag time par pahunchte hain. Is timing difference ko skew kehte hain.

Formula Parallel Bandwidth par Skew ka Limit

Ek $n$ wires wale parallel bus mein, agar kisi bhi do wires ke beech skew $Δ t_{s k e w}$ hai, toh maximum clock period hai: $T_{c l k} \geq Δ t_{s k e w} +_{se t u p} + t_{h o l d}$

First principles se Derivation:

Receiver sabhi $n$ bits ko ek clock edge se sample karta hai
Sahi sampling ke liye, sabhi bits stable honi chahiye setup/hold window ke dauran
Agar ek bit jaldi aaye aur doosri der se, toh farq $Δ t_{s k e w}$ clock period ko "khaa jaata" hai
Setup time $t_{se t u p}$ matlab clock edge se pehle kitni der data stable rehna chahiye
Hold time $t_{h o l d}$ matlab clock edge ke baad kitni der data stable rehna chahiye
Isliye: $T_{c l k} = t_{v a l i d} + t_{se t u p} + t_{h o l d}$ jahan $t_{v a l i d} \geq Δ t_{s k e w}$

Maximum frequency: $f_{ma x} = \frac{1}{T _{c l k}} \leq \frac{1}{Δ t _{s k e w} + t _{se t u p} + t _{h o l d}}$

Yeh kyun important hai: 10 cm trace length par, speed-of-light delay ~0.5 ns hai. 1 mm length mismatch ke saath, skew ~5 ps hai. 1 GHz par (period = 1 ns), 5 ps skew manageable hai. 10 GHz par (period = 0.1 ns = 100 ps), 5 ps clock period ka 5% hai — yeh acceptable nahi hai.

2. Crosstalk

Formula Crosstalk Voltage

Jab do parallel traces signals carry karte hain, aggressor line capacitive aur inductive coupling ke zariye victim line par voltage induce karta hai: $V_{cr oss t a l k} \approx C_{m u t u a l} \frac{d V _{a g g r essor}}{d t}$ Derivation:

Do parallel traces mein mutual capacitance $C_{m u t u a l}$ hoti hai (pF/cm range)
Aggressor mein current: $i_{a g g r essor} = C_{m u t u a l} \frac{d V}{d t}$ (displacement current)
Yeh victim trace ke through return karta hai, uski impedance par voltage drop cause karta hai
Fast edges ke liye (high $\frac{d V}{d t}$ ), crosstalk voltage linearly badhti hai Yeh parallel ko kyun khatam karta hai: Jab 8 ya 64 lines ek saath switch karti hain, crosstalk data-dependent hoti hai. Pattern "0101" maximum crosstalk cause karta hai. Tumhe edges slow karni padti hain ( $\frac{d V}{d t} ↓$ ), jo bandwidth limit karta hai.

3. Electromagnetic Interference (EMI)

Parallel buses jisme kaafi saari traces ek saath switch karti hain, antennas ki tarah kaam karti hain. Radiated power frequency aur simultaneous edges ki sankhya ke saath scale karti hai:

$P_{r a d ia t e d} \propto f^{2} \cdot n \cdot l^{2}$

jahan $n$ = traces ki sankhya, $l$ = trace length, $f$ = frequency. FCC limits designers ko shielding/filtering add karne par majboor karti hain, jisse cost badhti hai.

Serial ka Solution

Differential pairs ke saath serial signaling teeno problems solve karta hai:

Koi skew nahi: Sirf 1 data lane (aur uska complement), isliye koi multi-wire alignment problem nahi
Differential immunity: Crosstalk common-mode noise ki tarah appear karta hai, receiver dwara reject ho jaata hai
Kam EMI: Differential currents cancel ho jaate hain, radiation kam karte hain

Formula Serial Bandwidth Calculation

Ek serial link jo symbol rate $R_{s}$ (Gbaud) par chal raha hai, encoding overhead $η$ ke saath data rate achieve karta hai: $R_{d a t a} = R_{s} \cdot η \cdot b$ jahan $b$ = bits per symbol (usually NRZ ke liye 1, PAM-4 ke liye 2).

Derivation:

Symbol rate $R_{s}$ matlab per second voltage transitions ki sankhya
Har symbol $b$ bits of information carry karta hai (voltage levels ka log₂)
Encoding (8b/10b, 64b/66b) overhead add karta hai: har $k$ data bits ke liye, hum $n$ encoded bits bhejte hain
Efficiency $η = \frac{k}{n}$ (8b/10b: $η = 0.8$ ; 64b/66b: $η = 0.97$ ) Example: PCIe Gen3, 128b/130b encoding ke saath 8.0 GT/s (gigatransfers/sec) use karta hai: $R_{d a t a} = 8.0 \times 1 0^{9} \times \frac{128}{130} \times 1 \approx 7.877 Gbps per lane$

16 lanes (x16): $16 \times 7.877 \approx 126$ Gbps total — manageable pin count ke saath parallel buses se kaafi zyada.

SerDes kaise kaam karta hai

Serializer Architecture

Figure — Serial vs parallel signaling (SerDes)

Step-by-step operation:

Parallel Load: Slow clock $f_{l o w}$ par, $n$ bits shift register mein load karo
Fast Clock Multiplication: PLL $f_{hi g h} = n \cdot f_{l o w}$ generate karta hai
Shift Out: Har $f_{hi g h}$ cycle mein, differential TX lines par 1 bit shift out karo
Differential Driver: Single-ended logic ko differential voltage mein convert karta hai (jaise ±400 mV)

Deserializer Architecture

Receiver ko yeh karna hota hai:

Clock Recover karo: Incoming data mein alag clock wire nahi hoti. Data edges se clock extract karne ke liye CDR use karo.
Data Sample karo: Maximum margin ke liye mid-bit par sample karo (transitions par nahi).
Byte Boundary se Align karo: Special patterns (8b/10b mein comma characters) use karke har $n$ -bit group ka start dhundho.

Parallel vs. Serial kab use karein

Criterion	Parallel	Serial (SerDes)
Frequency	< 500 MHz	> 1 GHz
Distance	< 10 cm (on-chip, PCB)	cm se meters tak
Pin count	Zyada (8, 16, 64 wires)	Kam (1 diff pair = 2 pins)
Cost	Kam (simple logic)	Zyada (PLL, CDR, analog)
Power	Low speed par kam	Zyada (high-speed analog)
Use cases	DRAM interfaces (DDR), on-chip buses	PCIe, USB, SATA, Ethernet, chiplet I/O

Common Mistakes

Active Recall Prompts

Recall SerDes ko ek 12-saal ke bachhe ko explain karo

Socho tum ek kamre se doosre mein 10 books ki stack le ja rahe ho. Tumhare paas do choices hain: Option 1 (Parallel): Ek hi baar mein saari 10 books uthao. Fast, hai na? Lekin stack bhaari aur hilti hai — tum unhe gira sakte ho, aur tumhe wide doorway chahiye.

Option 2 (Serial): Ek baar mein 1 book le jao, lekin bahut tez bhaago. Haan, tum 10 trips lete ho, lekin tum itne fast ho ki "saari 10 books ek saath" wala banda door se guzrne se pehle hi tum finish kar lete ho. Plus, kabhi kuch girta nahi kyunki 1 book control karna easy hai.

SerDes Option 2 hai. Computers pehle Option 1 ki tarah data bhejte the (parallel wires, ek saath kaafi bits), lekin wires sanki galiyon ki tarah hain — woh ek doosre se interfere karti hain, "dropped books" (errors) cause karti hain. Toh ab hum ek bit ek waqt mein (serial) ek single super-fast wire par bhejte hain. Trick yeh hai ki "serializer" bits ko ek single stream mein pack karta hai, aur "deserializer" doosre end par unhe unpack karta hai. Yeh faster hai, kam wires hain, aur kam galtiyan hain!

Connections

Clock Domain Crossing (CDC): SerDes deserializer ek naya clock domain create karta hai; system clock mein cross karne ke liye FIFOs chahiye.
PCIe Protocol: 128b/130b encoding ke saath SerDes use karta hai; lanes gang kiye ja sakte hain (x1, x4, x16).
Eye Diagrams: SerDes link quality measure karne ka visual tool (jitter, noise, ISI).
Equalization (CTLE, DFE): High-speed SerDes, PCB traces se ISI combat karne ke liye equalization use karta hai.
8b/10b Encoding: Common SerDes encoding scheme; DC balance aur comma symbols ke liye 20% bandwidth trade karta hai.
PLL and Clock Synthesis: Serializer ko clock multiply karne ke liye PLL chahiye; deserializer CDR ek PLL ka form hai.
Differential Signaling: SerDes almost hamesha differential pairs use karta hai (LVDS, CML).
DDR Memory Interface: Skew manage karne ke liye source-synchronous clocking ke saath parallel signaling use karta hai.

#flashcards/hardware

High frequencies par serial signaling ka parallel par kya key advantage hai? :: Serial, multiple wires par skew accumulation avoid karta hai, ek single differential pair par bahut zyada higher bit rates allow karta hai.

SerDes ka full form kya hai aur yeh kya karta hai?

Serializer-Deserializer; parallel data ko transmission ke liye high-speed serial mein convert karta hai aur receiver par wapas parallel mein.

~1 GHz se upar parallel bus skew kyun unmanageable ho jaata hai?

1 GHz par, period = 1 ns. Trace length mismatch se sirf 10 ps skew (period ka 1%) bhi setup/hold margin consume kar leta hai. 10 GHz par, 10 ps period ka 10% hai — impractical.

Clock-Data Recovery (CDR) kya hai aur SerDes mein yeh kyun zaroori hai?

CDR, edges detect karke incoming serial data stream se clock extract karta hai. Zaroori hai kyunki serial links alag clock wire nahi bhejte — pin count aur skew kam hota hai.

Differential signaling SerDes mein crosstalk reduce karne mein kaise help karta hai?

Paas ki traces ka crosstalk differential pair ki dono wires par common-mode noise ki tarah appear karta hai. Receiver dono signals subtract karta hai, common-mode cancel karta hai aur sirf differential signal preserve karta hai.

Encoding overhead wale serial link ka data rate formula kya hai?

R_{d a t a} = R_{s} \cdot η \cdot b

jahan

R_{s}

symbol rate hai,

η

encoding efficiency hai (jaise 128b/130b ke liye 128/130), aur

b

bits per symbol hai (NRZ ke liye 1, PAM-4 ke liye 2).

Parallel buses ke liye EMI radiated power

f^{2} \cdot n \cdot l^{2}

ke saath kyun scale karta hai?

Higher frequency

f

matlab faster current changes (zyada antenna efficiency),

n

traces

n

antennas ki tarah kaam karte hain, aur lambi trace length

l

effective antenna aperture badhati hai. Har factor saath milke multiply hota hai.

Parallel se serial mein industry crossover kis approximate frequency par hota hai aur kyun?

Lagbhag 500 MHz se 1 GHz ke beech. Isse neeche, parallel sasta hai. Isse upar, skew aur crosstalk SerDes cost ke comparison mein parallel ko impractical bana dete hain.