Clock domain crossing

WHAT is a clock domain?

WHY it's dangerous: every flip-flop needs its input D to be stable for a window around the capturing clock edge:

setup time $t_{su}$ — data stable before the edge,
hold time $t_{h}$ — data stable after the edge.

If the source domain changes the signal inside this window (which is unavoidable when clocks are unrelated), the flip-flop enters metastability.

WHAT is metastability?

HOW long does metastability last? (Derivation)

Near the peak the flip-flop behaves like a regenerative amplifier: a small voltage imbalance $v$ grows exponentially because the two cross-coupled inverters amplify each other. Model:

$\frac{dv}{dt} = \frac{v}{\tau}$

Why this step? The loop gain is positive feedback with a characteristic time constant $\tau$ (set by transistor $g_m$ and load $C$ : $\tau \approx C/g_m$ ). Solving:

$v(t) = v_0\, e^{\,t/\tau}$

The output is "resolved" once $v(t)$ reaches a valid logic swing $V_{logic}$ . If we assume the initial imbalance $v_0$ is uniformly distributed over the metastability window, the probability the ball is still on the peak after we wait a settling time $t_s$ is

$P(\text{unresolved after } t_s) \propto e^{-t_s/\tau}.$

Caveat (be honest): real devices do not have a perfectly uniform $v_0$ distribution, so the exact constant in front of $e^{-t_s/\tau}$ differs from the naive uniform-model value. In practice this constant is folded into the empirical fitting parameter $T_0$ , which is measured on silicon — the exponential shape survives, only the prefactor is calibrated.

Combining with how often we enter metastability (rate $\propto f_{clk}\,f_{data}\,T_0$ ), we get the master reliability formula.

Formula Mean Time Between Failures (MTBF)

$\boxed{\;\text{MTBF} = \dfrac{e^{\,t_s/\tau}}{T_0 \, f_{clk}\, f_{data}}\;}$

$t_s$ = time we allow the signal to settle before using it (one extra flop = one clock period),
$\tau$ = regeneration time constant of the flop (technology-dependent, ~tens of ps),
$T_0$ = a fitting constant (metastability "aperture", ~ps) that also absorbs the real (non-uniform) $v_0$ distribution — it is measured, not derived,
$f_{clk}$ = sampling clock frequency, $f_{data}$ = rate of asynchronous input changes.

WHY exponential: each extra bit of settling time $t_s$ multiplies reliability, so adding even one clock period of settling makes MTBF astronomically large. This is why the fix is cheap and effective.

The fix #1 — Two-Flop Synchronizer (for single-bit signals)

HOW it works, step by step:

Async signal enters FF1. FF1 might catch it mid-transition → metastable. Why? Setup/hold violated because the source is unrelated.
We wait for FF1 to resolve. The available settling time is $t_s = T_{clk} + t_{cq,FF1} - t_{su,FF2},$ Why this exactly? Start counting from the clkB edge that put FF1 into metastability. FF1's resolved value only appears at its output after its clock-to-Q delay $t_{cq,FF1}$ , which effectively extends the window; FF2 must see stable data one setup time $t_{su,FF2}$ before the next clkB edge (one full period $T_{clk}$ later). Netting these three gives the formula above. (A common simplification drops $t_{cq,FF1}$ , but strictly it belongs there.)
FF2 samples FF1's (resolved) output. Why safe now? Plug this larger $t_s$ into MTBF → the exponential makes failure vanishingly rare.

The fix #2 — Multi-bit crossings

Gray code (for pointers/counters)

Handshake (for arbitrary data words)

Sender puts data on a bus, raises req. req (1 bit) is synchronized into the receiver. Receiver latches data (now stable), raises ack. ack (1 bit) is synchronized back. Only control bits cross with synchronizers; the data bus is held stable and never sampled during transition.

Asynchronous FIFO

Dual-port RAM + Gray-coded read/write pointers each synchronized into the opposite domain. The gold standard for high-throughput CDC.

Recall Feynman: explain to a 12-year-old (click to reveal)

Imagine passing a glass of water to a friend who's on a spinning merry-go-round. If you let go at the wrong moment, the glass tips and spills — you can't read how full it is anymore. A synchronizer is like waiting one full spin so the glass settles in your friend's hand before you check the level. And if you're passing a whole tray of glasses (many bits), you don't toss them one by one — you say "ready?" and only hand them over when your friend says "got it!" That "ready/got-it" chat is the handshake.

Worked examples

Worked example Example 1 — MTBF with one vs two synchronizer stages

Given: $\tau = 50\text{ ps}$ , $T_0 = 20\text{ ps}$ , $f_{clk}=100\text{ MHz}$ , $f_{data}=10\text{ MHz}$ , destination period $T=10\text{ ns}$ . Take $t_{cq,FF1}\approx t_{su,FF2}$ so the settling window is one period $t_s \approx 10\text{ ns}$ .

= \frac{e^{10\text{ns}/50\text{ps}}}{20\text{ps}\cdot 10^8 \cdot 10^7} = \frac{e^{200}}{2\times10^4}.$$ $e^{200}\approx 7\times10^{86}$ → MTBF $\approx 3.6\times10^{82}$ s ≈ far longer than the age of the universe. **Why this step?** The ratio $t_s/\tau=200$ dominates; the exponential crushes everything. **Lesson:** one extra flop (one period of $t_s$) is enough for near-perfect reliability.

Flashcards

What is a clock domain crossing?

A signal made in one clock domain being sampled by flip-flops in another, asynchronous, clock domain.

Why does CDC cause problems?

The source can change the signal inside the destination flop's setup/hold window, causing metastability.

Define metastability.

A flip-flop output stuck at an invalid voltage between 0 and 1 for a random time before resolving unpredictably.

Can a synchronizer eliminate metastability?

No — it only reduces its probability (increases MTBF); metastability is a physical inevitability.

State the MTBF formula.

MTBF = e^(t_s/τ) / (T₀ · f_clk · f_data).

What is the available settling time in a two-flop synchronizer?

t_s = T_clk + t_cq,FF1 − t_su,FF2 (period plus FF1's clock-to-Q, minus FF2's setup).

In the MTBF formula, what does τ represent?

The regeneration (resolution) time constant of the flip-flop; smaller τ resolves faster.

Why is MTBF exponential in t_s?

Metastability decays exponentially (dv/dt = v/τ ⇒ v = v₀ e^{t/τ}), so waiting longer multiplies reliability.

What does T₀ physically absorb besides the metastability aperture?

The real (non-uniform) v₀ distribution — T₀ is a measured fitting constant, not derived.

How does a two-flop synchronizer help?

FF1 absorbs metastability and gets ~one full clock period to settle before FF2 samples the resolved value.

Why must you NOT synchronize each bus bit independently?

Bits resolve on different cycles, so the receiver can read a value that never actually existed (data incoherence).

How do you safely cross a multi-bit counter?

Encode it in Gray code so only one bit changes per step; worst case read is off-by-one but always valid.

How do you cross an arbitrary data word?

Use a handshake (sync req/ack control bits, hold data stable) or an asynchronous FIFO.

What two timing constraints define the danger window?

Setup time (data stable before edge) and hold time (data stable after edge).

Connections

Flip-flops and setup-hold time
Metastability
Gray code
Asynchronous FIFO design
Handshake protocols
Clock skew and jitter
Synchronous vs asynchronous circuits

Concept Map

Hinglish (regional understanding)

Intuition Hinglish mein samjho

Socho do alag-alag clocks hain — clock A aur clock B — jo bilkul unrelated speed pe chal rahe hain. Jab A domain ka koi signal B domain ke flip-flop me jata hai, tab problem hoti hai: har flip-flop ko chahiye ki uska input clock edge ke aas-paas kuch time (setup aur hold time) stable rahe. Lekin async clocks me source signal kisi bhi random moment pe change kar sakta hai, exactly capture window ke andar. Result: metastability — output na 0 hota hai na 1, beech me atak jata hai aur random time me resolve hota hai. Ye "ball on the hill" jaisa hai — girega zaroor, par kab, ye pata nahi.

Iska fix simple aur sasta hai: two-flop synchronizer. Pehla flop (FF1) metastable ho sakta hai, par usko poora ek destination clock period milta hai settle hone ke liye. Exact available settling time hoti hai t_s = T_clk + t_cq,FF1 - t_su,FF2 — yaani ek period, plus FF1 ka clock-to-Q delay (jo window ko thoda badha deta hai), minus FF2 ka setup time. Fir doosra flop (FF2) us settled value ko sample karta hai. MTBF formula, MTBF = e^(t_s/τ) / (T0·f_clk·f_data), batata hai ki thoda sa extra settling time exponentially reliability badha deta hai — isliye ek extra flop lagane se failure practically namumkin ho jata hai (universe ki age se bhi zyada MTBF). Yaad rakho: T0 sirf ek measured fitting constant hai, jo real (non-uniform) v0 distribution ko bhi absorb kar leta hai.

Bada point: single bit ke liye two-flop chalta hai, par multi-bit bus ke liye NAHI. Agar har bit ko alag se sync karoge, to alag-alag bits alag cycle pe aayenge aur receiver aisa value padh lega jo kabhi exist hi nahi karta (data incoherence). Isliye counters ke liye Gray code use karo (ek time me sirf ek bit change), aur arbitrary data ke liye handshake ya async FIFO — jahan sirf control bits (req/ack) sync hote hain aur data bus stable rehta hai. Ye discipline hi real chips me har jagah lagti hai, isliye exam aur job dono me CDC bahut important topic hai.

WHAT is a clock domain?

WHAT is metastability?

HOW long does metastability last? (Derivation)

The fix #1 — Two-Flop Synchronizer (for single-bit signals)

The fix #2 — Multi-bit crossings

Gray code (for pointers/counters)

Handshake (for arbitrary data words)

Asynchronous FIFO

Worked examples

Flashcards

Connections

Concept Map

Hinglish (regional understanding)

Go deeper — visual, from zero

Test yourself — Sequential Circuits

Connections