Clock domain crossing

3.4.14 · Hardware › Sequential Circuits

WHAT hai ek clock domain?

WHY yeh dangerous hai: har flip-flop ko apni input D capturing clock edge ke ird-gird ek window mein stable rehna chahiye:

• setup time $t_{su}$ — data edge se pehle stable,
• hold time $t_h$ — data edge ke baad stable.

Agar source domain signal ko is window ke andar badal de (jo tab inevitable hai jab clocks unrelated hon), to flip-flop metastability mein chala jaata hai.

WHAT hai metastability?

HOW lamba rehta hai metastability? (Derivation)

Peak ke paas flip-flop ek regenerative amplifier ki tarah behave karta hai: ek chhota voltage imbalance $v$ exponentially badhta hai kyunki do cross-coupled inverters ek doosre ko amplify karte hain. Model:

$\frac{dv}{dt}=\frac{v}{\tau }$

Yeh step kyun? Loop gain positive feedback hai ek characteristic time constant $\tau$ ke saath (jo transistor $g_m$ aur load $C$ se set hota hai: $\tau \approx C/g_m$). Solve karne par:

$v(t)=v_0{e}^{t/\tau }$

Output "resolved" maana jaata hai jab $v(t)$ ek valid logic swing $V_{logic}$ tak pahunch jaata hai. Agar hum assume karein ki initial imbalance $v_0$ metastability window par uniformly distributed hai, to probability ki ball settling time $t_s$ ke baad bhi peak par hai:

$P(\text{unresolved after }{t}_s)\propto e^{-t_s/\tau }.$

Caveat (honestly bolein): real devices mein $v_0$ distribution perfectly uniform nahi hoti, isliye $e^{-t_s/\tau }$ ke aage ka exact constant naive uniform-model value se alag hota hai. Practice mein yeh constant empirical fitting parameter $T_0$ mein fold ho jaata hai, jo silicon par measure kiya jaata hai — exponential shape survive karti hai, sirf prefactor calibrate hota hai.

Is cheez ko combine karo ki hum kitni baar metastability mein jaate hain (rate $\propto f_{clk}{f}_{data}{T}_0$), to hum master reliability formula paate hain.

Fix #1 — Two-Flop Synchronizer (single-bit signals ke liye)

HOW kaam karta hai, step by step:

1. Async signal FF1 mein enter karta hai. FF1 use mid-transition pakad sakta hai → metastable. Kyun? Setup/hold violate hua kyunki source unrelated hai.
2. Hum FF1 ko resolve hone dete hain. Available settling time hai: $t_s=T_{clk}+t_{cq,FF1}-t_{su,FF2},$ Yeh exactly kyun? clkB edge se count karna shuru karo jo FF1 ko metastability mein daal gayi. FF1 ki resolved value uske output par sirf uske clock-to-Q delay $t_{cq,FF1}$ ke baad appear hoti hai, jo effectively window ko extend karti hai; FF2 ko agale clkB edge (ek poora period $T_{clk}$ baad) se ek setup time $t_{su,FF2}$ pehle stable data dekhna chahiye. In teeno ko net karne par upar wala formula milta hai. (Ek common simplification $t_{cq,FF1}$ drop kar deti hai, lekin strictly yeh wahan hona chahiye.)
3. FF2, FF1 ka (resolved) output sample karta hai. Ab safe kyun? Is bade $t_s$ ko MTBF mein plug karo → exponential failure ko vanishingly rare bana deta hai.

Fix #2 — Multi-bit crossings

Gray code (pointers/counters ke liye)

Handshake (arbitrary data words ke liye)

Sender data bus par rakhta hai, req raise karta hai. req (1 bit) ko receiver mein synchronized kiya jaata hai. Receiver data latch karta hai (ab stable hai), ack raise karta hai. ack (1 bit) ko wapas synchronized kiya jaata hai. Sirf control bits synchronizers se cross karte hain; data bus stable rakha jaata hai aur transition ke dauran kabhi sample nahi hota.

Asynchronous FIFO

Dual-port RAM + Gray-coded read/write pointers jo opposite domain mein synchronized hote hain. High-throughput CDC ka gold standard.

Worked examples

Flashcards

Connections

• Flip-flops and setup-hold time
• Metastability
• Gray code
• Asynchronous FIFO design
• Handshake protocols
• Clock skew and jitter
• Synchronous vs asynchronous circuits

Concept Map