Clock tree synthesis — Hinglish notes

4.2.7 · Hardware › VLSI Design

WHAT is CTS?

CTS se pehle, clock ek ideal net hota hai (zero delay assume kiya jaata hai). CTS ke baad, woh ek real tree ban jaata hai buffers, real wire RC, aur real arrival times ke saath.

Root = clock source (PLL output / clock port).
Leaves/Sinks = flip-flops, latches, memories ke clock pins.
Internal nodes = inserted clock buffers/inverters.

The three key quantities (WHY they matter)

WHY skew villain hai: ek launching FF aur ek capturing FF ke beech timing directly unke clock arrival times ke difference par depend karti hai, absolute latency par nahi.

HOW skew aapka timing budget khaata hai (scratch se derive karo)

Maano data FF1 (clock arrival $t_{1}$ ) se launch hota hai aur FF2 (clock arrival $t_{2}$ ) se capture hota hai, ek clock period $T$ ke baad.

Setup check (data agli edge se pehle pahunchna chahiye):

Data FF1 se $t_{1} + t_{c q}$ par nikalta hai (clock-to-Q), combinational logic $t_{l o g i c}$ se guzarta hai, aur FF2 ki capturing edge $t_{2} + T$ se pehle setup time $t_{s u}$ satisfy karni chahiye:

$t_{1} + t_{c q} + t_{l o g i c} + t_{s u} \leq t_{2} + T$

Rearrange karo, skew $= t_{2} - t_{1}$ let karte hue:

$t_{c q} + t_{l o g i c} + t_{s u} \leq T + (t_{2} - t_{1})$

Hold check (data itna jaldi nahi aana chahiye ki same edge use capture kar le):

$t_{1} + t_{c q} + t_{c d} \geq t_{2} + t_{h o l d}$

jahan $t_{c d}$ minimum (contamination) logic delay hai. Rearrange karne par:

$t_{c q} + t_{c d} \geq t_{h o l d} + (t_{2} - t_{1})$

HOW CTS actually tree banata hai

Common structures:

H-tree / X-tree — ek geometrically symmetric fractal. Har leaf root se same wire distance par hoti hai ⇒ naturally low skew. Regular arrays ke liye badhiya (jaise CPUs ki clock spines), irregular placements ke liye wasteful.
Buffered clock tree (algorithmic) — tools nearby sinks ko cluster karte hain, load balance karne ke liye buffers insert karte hain, aur recursively merge karte hain. Classic algorithm hai DME (Deferred-Merge Embedding), jo zero-skew merging par based hai.

Zero-skew merge point (balance derive karo)

Do subtrees jinke sinks tak delays $d_{1}$ aur $d_{2}$ hain, join ki jaati hain. Hum merge point ko ek wire of total length $L$ ko $l_{1}$ (node 1 tak) aur $l_{2} = L - l_{1}$ (node 2 tak) mein split karke place karte hain. Length $l$ wale wire segment ke liye Elmore delay use karte hue, resistance $r$ aur capacitance $c$ per unit length ke saath load cap $C$ drive karte hue:

$t_{w i r e} (l, C) = r l (\frac{c l}{2} + C)$

Zero skew ke liye hum chahte hain ki merge point se dono sides ka delay equal ho:

$d_{1} + t_{w i r e} (l_{1}, C_{1}) = d_{2} + t_{w i r e} (l_{2}, C_{2})$

Substitute karke aur dono delays equal set karne par merge-point location $l_{1}$ milta hai (ek quadratic solve karke). $\frac{c l ^{2}}{2}$ self term ignore karne wale simplified case ke liye:

$d_{1} + r l_{1} C_{1} = d_{2} + r l_{2} C_{2}, l_{1} + l_{2} = L$ $\Rightarrow l_{1} = \frac{( d _{2} - d _{1} ) + r L C _{2}}{r ( C _{1} + C _{2} )}$

Worked Example 1 — Skew aur setup budget

Given: $T = 2 ns$ , $t_{c q} = 0.2$ , $t_{l o g i c} = 1.5$ , $t_{s u} = 0.1$ ns. Launch clock $t_{1} = 0.5$ par aata hai, capture $t_{2} = 0.6$ ns par.

Setup slack $= (T + t_{2} - t_{1}) - (t_{c q} + t_{l o g i c} + t_{s u})$

Yeh step kyun? Slack = available − required; positive matlab timing meet ho rahi hai.

$= (2 + 0.6 - 0.5) - (0.2 + 1.5 + 0.1) = 2.1 - 1.8 = + 0.3 ns$ ✅ setup meet karta hai.

Ab hold check karo $t_{c d} = 0.3$ , $t_{h o l d} = 0.15$ ns ke saath: Required: $t_{c q} + t_{c d} \geq t_{h o l d} + (t_{2} - t_{1})$ $0.2 + 0.3 = 0.5 \geq 0.15 + 0.1 = 0.25$ ✅ pass karta hai.

Yeh step kyun? Hume hold bhi same skew se verify karni chahiye — positive skew ne hold margin shrink kar diya.

Worked Example 2 — Zero-skew merge point

Given: Do sinks. Left ka accumulated delay $d_{1} = 40$ ps hai, right ka $d_{2} = 10$ ps. Wire per-unit $r = 0.1 Ω/ μ m$ , sink caps $C_{1} = C_{2} = 20 fF$ , total merge wire $L = 100 μ m$ .

$l_{1} = \frac{( d _{2} - d _{1} ) + r L C _{2}}{r ( C _{1} + C _{2} )}$ use karke:

Yeh step kyun? Hum woh split chahte hain jo root-to-sink delay equal kare.

Numerator (consistent units rakho, ps/fF/Ω/µm use karo): $r L C_{2} = 0.1 \times 100 \times 20 = 200$ (ps-like scaled units), $(d_{2} - d_{1}) = - 30$ . $l_{1} = \frac{- 30 + 200}{0.1 \times 40} = \frac{170}{4} = 42.5 μ m$

Toh merge point sink 1 se 42.5 µm door hai (slower side ko kam wire milti hai). Kyunki $0 \leq 42.5 \leq 100$ , koi snaking zaroorat nahi. ✅

Worked Example 3 — Kyun H-tree (near) zero skew deta hai

H-tree mein root se leaf tak har path construction se same number of segments of same lengths traverse karta hai. Kyunki delay sirf traversed RC par depend karti hai, equal geometry ⇒ equal delay ⇒ skew ≈ 0 (process variation ignore karte hue).

Yeh step kyun? Symmetry per-net balancing ki jagah le leti hai — yeh ek structural solution hai algorithmic ke mukable.

Active Recall

Recall Reveal karne se pehle khud explain karo

Insertion delay aur skew mein kya difference hai?
Positive skew setup ko help kyun karta hai lekin hold ko hurt kyun karta hai?
DME merge point fast ya slow subtree ki taraf move karta hai?
CTS power-critical kyun hai?

Recall Feynman: ek 12-saal ke bacche ko explain karo

Tum "sablog ek saath kudo!" khel rahe ho. Tum (boss) GO chillate ho. Lekin agar tumhare dost alag-alag dooriyon par khade hain, toh awaaz untak alag-alag waqt mein pahunchti hai, aur woh alag-alag time par koodte hain. Isko fix karne ke liye, tum helpers (buffers) rakhte ho jo woh word dobara chillate hain, aur tum paths ko equally lamba banate ho taaki word sabko saath mein pahunche. Unke sunne mein jo choti differences hain = skew. Tumse kisi dost tak signal ka total travel time = insertion delay. Yeh helpers aur equal paths ka network banana hi clock tree synthesis hai.

Connections

Static Timing Analysis — CTS clock arrivals ko real banata hai taaki STA accurate ho sake.
Setup and Hold Time — woh constraints jo CTS ko satisfy karni hain.
Elmore Delay Model — merge points ke peeche ka RC delay math.
Placement (VLSI) — sink locations placement se aati hain; CTS uske baad run hota hai.
Useful Skew / Clock Skew Scheduling — timing closure ke liye intentional skew.
Clock Gating and Power — CTS gated clock enables handle karta hai aur dynamic power dominate karta hai.
On-Chip Variation (OCV) — kyun real skew margins nominal skew se zyada hoti hain.

Clock Tree Synthesis kya hai?

Woh physical-design step jo source se sab flip-flop clock pins tak buffers insert karke aur clock net route karke skew aur insertion delay minimize karta hai, jabki slew/cap/fanout limits meet hon.

Insertion delay (clock latency) define karo.

Clock root se kisi given sink (leaf) tak clock edge propagate hone mein kitna time lagta hai.

Clock skew define karo.

Do flip-flops ke beech insertion delay (clock arrival time) ka difference; global skew = max latency − min latency.

Positive skew (capture launch se baad) setup ki help kyun karta hai?

Setup equation ban jaati hai

t_{c q} + t_{l o g i c} + t_{s u} \leq T + (t_{2} - t_{1})

, toh baad mein capture karna slack add karta hai.

Positive skew hold ko hurt kyun karta hai?

Hold require karta hai

t_{c q} + t_{c d} \geq t_{h o l d} + (t_{2} - t_{1})

; baad mein capture karna minimum data delay ki requirement badhaata hai.

H-tree kya hai aur uska skew low kyun hota hai?

Ek geometrically symmetric fractal clock distribution jisme har root-to-leaf path ki identical length/segments hoti hain, toh delays structurally match karte hain.

DME/zero-skew merging mein merge point kis taraf move karta hai?

Faster (smaller-delay) subtree ki taraf, taaki uska extra wire delay arrival times equal kare.

'Useful skew' kya hota hai?

Intentionally non-zero skew schedule karna taaki critical paths par time borrow kiya ja sake (setup ke liye capture delay karo, hold ke liye advance karo) instead of forced zero skew.

Clock tree power-critical kyun hai?

Yeh chip ka highest-toggling net hai; dynamic power

P = α C V^{2} f

matlab buffers aur clock cap switching power dominate karte hain.

CTS ke relative hold fixing typically kab hoti hai?

CTS ke baad, jab clock arrivals real ho jaati hain, data paths par delay buffers insert karke.

Length

l

(r,c per unit) ki wire ka Elmore delay do jo load C drive kare.

t = r l (c l /2 + C)