Floorplanning and power planning

Physical design stage where we decide where big blocks sit on the chip and how electrical power reaches every transistor before we place standard cells or route signals.

WHAT is Floorplanning?

Key outputs decided:

Core area and utilization (how packed the cells will be).
Aspect ratio (width : height of the core).
Macro locations and orientation.
Halo / keep-out regions around macros (blockages so cells don't crowd them).
Power grid skeleton (rings + straps).

WHY power planning happens here (and early)

Formula Electromigration current limit

WHY: Too much current density $J = I/(W\,t)$ (current per unit cross-sectional area $= W\times t$ ) physically erodes the metal over years (atoms drift → open circuit). Reliability sets a max $J_{max}$ in $\text{mA}/\mu m^2$ , so a strap of width $W$ and thickness $t$ can carry at most $I_{max} = J_{max}\cdot (W\cdot t)$ HOW: for a fixed process thickness $t$ , this becomes a per-unit-width current limit $I_{max}/W = J_{max}\,t$ (units $\text{mA}/\mu m$ ), which directly sets a minimum strap width for the current it must deliver — another reason grids use wide top metal. Keep $J_{max}$ (per area) and the derived per-width limit distinct.

Worked Examples

Common Mistakes (Steel-manned)

Flashcards

What are the four main things floorplanning decides?

Die/core size & aspect ratio, macro placement/orientation, I/O pad placement, and reserved routing channels + power grid skeleton.

Define core utilization.

(A_{cells}+A_{macros})/(A_{core}-A_{blockage})

— fraction of usable core area occupied.

Why keep early utilization around 65–75%?

To leave routing headroom; too high causes congestion and unroutable/DRC-violating designs.

Given target utilization U, how do you get core width for a square core?

A_{core}=A_{used}/U

, then

W=\sqrt{A_{core}}

(since

AR=1

State the IR-drop formula and each symbol.

\Delta V = IR = I R_\square (L/W)

;

I

=current,

R_\square

=sheet resistance,

L

=length,

W

=width.

Two ways to reduce IR drop in a power grid?

Increase strap width

W

(lower

R

) and add more parallel straps (effective

R/N

); also use thick top metals.

Why route the power grid on top thick metals?

They have low sheet resistance (low IR drop) and higher current limit (less electromigration).

What is electromigration and its width constraint?

Current-driven atomic drift erodes metal → opens; needs

I \le J_{max}(W t)

, i.e.

W \ge I/(J_{max}\,t)

, so current density stays under

J_{max}

(per cross-sectional area

Wt

Name the power grid hierarchy from edge to cell.

Power ring → straps/stripes → standard-cell rails → vias stitching them together.

Where should macros be placed and why?

At the core periphery with pins toward core, plus halos — to avoid routing shadows and congestion.

Recall Feynman: explain to a 12-year-old

Imagine drawing a plan for a video-game city before building it. First you decide how big the map is and where the huge buildings (the memory blocks) go — that's floorplanning. Then, before placing any little houses, you draw thick electric cables all around and across the city so every house can get power without the lights dimming — that's power planning. Thick cables and lots of them = strong power. Thin cables far away = dim, flickering lights (that's "IR drop"). Do the cables first, houses second!

Connections

Standard Cell Placement — happens after floorplan, fills the rows.
Clock Tree Synthesis — macro locations set the clock skew budget.
Routing and Congestion — utilization headroom decided here.
Ohms Law — root of the IR-drop derivation.
Sheet Resistance — $R_\square=\rho/t$ used for strap resistance.
Electromigration Reliability — sets minimum strap width.
Signal Integrity and IR Drop Analysis — verifies the grid post-planning.

Concept Map

Hinglish (regional understanding)

Intuition Hinglish mein samjho

Dekho, floorplanning matlab chip banane se pehle ka "city planning". Pehle decide karte hain ki die/core kitna bada hoga, uska shape (aspect ratio) kya hoga, aur bade blocks yaani macros (SRAM, PLL) kahan baithenge. Ye sab standard cells place karne se pehle hota hai. Ek important number hai utilization — core kitna bhara hai. Usko 65-75% ke aas-paas rakhte hain, kyunki agar 100% bhar diya to wires ke liye jagah hi nahi bachegi aur routing fail ho jayegi (congestion).

Ab power planning. Har gate current kheenchta hai, aur metal wire mein resistance hota hai, to Ohm's law se voltage gir jata hai: $\Delta V = IR$ . Isko IR drop kehte hain. Agar VDD zyada gir gaya to gates slow ya fail. Isliye pehle ek strong power grid banate hain: ring core ke around, uske andar straps (motai wali lines) top thick metal par, aur har cell row mein patli rails. Thick top metal isliye kyunki uska sheet resistance kam hota hai — IR drop kam.

IR drop kam karne ke do simple tarike: strap ki width badhao (R kam hota hai) aur zyada straps parallel mein daalo (effective R = R/N). Dono seedha $\Delta V=IR$ pe attack karte hain. Ek aur cheez — electromigration: current density $J=I/(W t)$ yaani current divided by cross-sectional area (width $\times$ thickness). Agar $J$ bahut zyada ho gayi to years mein metal atoms shift ho ke wire tut jayegi. Isliye minimum width bhi maintain karni padti hai: $W \ge I/(J_{max}\,t)$ , jisme $t$ process ki fixed thickness hai.

Yaad rakho: power grid pehle, cells baad mein — jaise city mein bijli-paani ki pipeline pehle bichhate hain, ghar baad mein. Yehi core intuition hai jo interviews aur design dono mein kaam aayegi.

The Big Picture

WHAT is Floorplanning?

WHY power planning happens here (and early)

Worked Examples

Common Mistakes (Steel-manned)

Flashcards

Connections

Concept Map

Hinglish (regional understanding)

Test yourself — VLSI Design

Connections