4.2.6
Physical design ka woh stage jahan hum decide karte hain ki chip pe bade blocks kahan baithenge aur electrical power kaise har transistor tak pahunchegi — standard cells place karne ya signals route karne se pehle .
Intuition Ek city banane ke baare mein sochoFloorplanning bilkul city zoning map banane jaisi hai: factory (bade macros/RAM) kahan jaayegi, neighborhoods (standard-cell rows) kahan hongi, aur parks (khaali channels) kahan rahenge. Power planning uss city mein pehle paani aur bijli ka grid bichhane jaisi hai, taaki har ghar ko guaranteed connection mile. Agar pehle ghar banao aur pipes baad mein, toh sab kuch kharaab ho jaata hai. Isliye VLSI mein hum grid jaldi karte hain.
Floorplanning woh physical-design step hai jo chip ki die/core size , macros ki placement (bade pre-designed blocks jaise SRAM, PLLs, IP), I/O pads ki shape aur location , aur routing channels ka reservation fix karti hai — detailed cell placement se pehle.
Key outputs jo decide hote hain:
Core area aur utilization (cells kitni tightly packed hongi).Aspect ratio (core ki width : height).Macro locations aur orientation.Halo / keep-out regions macros ke around (blockages taaki cells unhe crowd na karein).Power grid skeleton (rings + straps).
Intuition IR-drop ki kahaniHar logic transition supply se current kheenchti hai. Metal wires mein resistance R drop karti hai: Δ V = I R low-resistance, wide, redundant power network banana padta hai — aur hum thin signal wires uske aaspaas tabhi route kar sakte hain jab grid pehle se exist kare.
Definition Power grid components
Power ring : core ke edge ke around VDD aur VSS ki wide metal loop — "highway on-ramp" jo I/O pads se feed hoti hai.Power straps (stripes): upper metals pe parallel VDD/VSS lines jo core ke through cross karti hain aur ring ko tap karti hain.Standard-cell rails : har cell row ke along thin M1 VDD/VSS lines.Vias / stacks : vertical connections jo straps → rails ko stitch karti hain.
Worked example 1 — Core sizingCells area = 6 mm 2 = 2 mm 2 U = 0.65 A R = 1
A core = ( 6 + 2 ) /0.65 = 12.31 mm 2 Kyun? Utilization = used / core ⇒ core = used / U.W = 12.31/1 = 3.51 mm H = 3.51 mm Square kyun? A R = 1 W = H = A
Worked example 2 — Ek strap pe IR dropEk VDD strap: R □ = 0.05 Ω/ □ L = 2000 μ m W = 2 μ m I = 8 m A
R = 0.05 × ( 2000/2 ) = 0.05 × 1000 = 50 Ω Kyun? L / W Δ V = I R = 0.008 × 50 = 0.4 V Kyun care karein? 1.0 V bahut zyada! Neeche fix karte hain.
Worked example 3 — Example 2 ko width + parallel straps se fix karnaW = 8 μ m R = 0.05 × ( 2000/8 ) = 12.5 Ω Δ V = 0.008 × 12.5 = 0.1 V Δ V = 0.1/4 = 0.025 V = 2.5% Yeh step kyun? Wider W R N R N Δ V = I R
Worked example 4 — Electromigration checkJ ma x = 2 m A / μ m 2 per unit cross-sectional area ), metal thickness t = 0.5 μ m I = 10 m A
Pehle thickness ko per-width limit mein fold karo: J ma x t = 2 × 0.5 = 1 m A / μ m Kyun? Cross-section = W t I ma x = J ma x ( W t ) ⇒ I ma x / W = J ma x t
W min = J ma x t I = 1 10 = 10 μ m Kyun? I ≤ J ma x ( W t ) W J ma x
Common mistake "Higher utilization hamesha better hoti hai — zyada logic pack hoti hai!"WHY it feels right: chhota die = sasta, aur 100% "used" silicon efficient lagta hai.
The flaw: routing ko cells ke beech jagah chahiye. ~80% se zyada early utilization pe router wires fit nahi kar sakta → congestion , DRC violations, timing failure. Fix: ~65% se start karo, routing headroom chhoddo; utilization tab badhao jab routing clean ho.
Common mistake "Power ko thin lower metals pe route karo taaki top layers signals ke liye bach jayein."WHY it feels right: signals ko bhi fast, low-cap top metals chahiye hote hain.
The flaw: lower metals mein high R □ hota hai ⇒ bada IR drop + electromigration failure. Power ko zaroor thick top metals use karne chahiye (low R □
Common mistake "Macros kahi bhi place karo; placer baad mein cells sort kar lega."WHY it feels right: macros sirf bade blocks hain.
The flaw: macros routing shadows aur pin-access problems create karte hain. Random placement → detours, congestion, long clock paths. Fix: macros ko periphery pe push karo, pins core ki taraf, halos add karo, power straps ke align karo.
Floorplanning jinhe decide karti hai woh chaar main cheezein kya hain? Die/core size aur aspect ratio, macro placement/orientation, I/O pad placement, aur reserved routing channels + power grid skeleton.
Core utilization define karo. ( A ce l l s + A ma cr os ) / ( A cor e − A b l oc k a g e )
Early utilization ~65–75% kyun rakhte hain? Routing headroom ke liye; bahut zyada hone par congestion aur unroutable/DRC-violating designs aate hain.
Target utilization U diya ho toh square core ke liye core width kaise milegi? A cor e = A u se d / U , phir
W = A cor e (kyunki
A R = 1 ).
IR-drop formula aur har symbol batao. Δ V = I R = I R □ ( L / W ) I R □ L W
Power grid mein IR drop kam karne ke do tarike? Strap width W R R / N
Power grid ko top thick metals pe kyun route karte hain? Unka sheet resistance kam hota hai (low IR drop) aur current limit zyada hoti hai (electromigration kam).
Electromigration kya hai aur iska width constraint kya hai? Current-driven atomic drift metal ko erode karta hai → opens; zaroorat hai I ≤ J ma x ( W t ) W ≥ I / ( J ma x t ) J ma x W t
Edge se cell tak power grid hierarchy batao. Power ring → straps/stripes → standard-cell rails → vias jo inhe stitch karti hain.
Macros kahan place karne chahiye aur kyun? Core ke periphery pe, pins core ki taraf, plus halos — routing shadows aur congestion avoid karne ke liye.
Recall Feynman: ek 12-saal ke bachche ko samjhaoImagine karo ki build karne se pehle ek video-game city ka plan draw kar rahe ho. Pehle tum decide karte ho ki map kitna bada hai aur huge buildings (memory blocks) kahan jaayengi — yeh hai floorplanning . Phir, koi bhi chhota ghar place karne se pehle, tum city ke chaaron taraf aur cross mein thick electric cables draw karte ho taaki har ghar ko power mil sake bina lights dim hue — yeh hai power planning . Thick cables aur bahut saari = strong power. Thin cables door se = dim, flickering lights (yahi "IR drop" hai). Pehle cables, phir ghar!
F loorplan sets: A rea, R atio (aspect), M acros.
Power grid: P ads → I ring → E straps → R ails. (Pads Ring ko feed karte hain, Ring strAps ko feed karta hai, strAps Rails ko feed karte hain.)
Standard Cell Placement — floorplan ke baad hota hai, rows fill karta hai.Clock Tree Synthesis — macro locations clock skew budget set karte hain.Routing and Congestion — utilization headroom yahan decide hota hai.Ohms Law — IR-drop derivation ki root.Sheet Resistance — R □ = ρ / t Electromigration Reliability — minimum strap width set karta hai.Signal Integrity and IR Drop Analysis — planning ke baad grid verify karta hai.
formula U = used / core - blockage
Core size and utilization
Signal routing around grid