Low-power design techniques (clock - power gating)

WHY does a CMOS chip burn power at all?

Before any technique, we must know what we are fighting. Total power splits into:

$P_{total} = P_{dynamic} + P_{short} + P_{static}$

Dynamic (switching) power — derived from scratch

Derivation (WHY the famous formula holds):

Charge stored on the cap when charged to $V_{dd}$ : $Q = C_L V_{dd}$

Energy drawn from the supply during one charge (supply held at $V_{dd}$ ): $E_{supply} = Q V_{dd} = C_L V_{dd}^2$

Half of that is stored on the cap ( $\tfrac12 C_L V_{dd}^2$ ), half is burned in the pull-up resistance. On the next discharge, the stored half is burned in the pull-down. So one full 0→1→0 cycle dissipates $C_L V_{dd}^2$ .

If the node makes $f$ full cycles per second and only actually switches with probability $\alpha$ (the activity factor), then:

$\boxed{P_{dynamic} = \alpha \, C_L \, V_{dd}^2 \, f}$

Static (leakage) power

Even a transistor that is "off" leaks subthreshold current $I_{leak}$ : $P_{static} = V_{dd}\, I_{leak}$ This dominates in modern nodes and does not depend on switching — an idle block still leaks. This is precisely why we need power gating.

Technique 1: Clock Gating (attacks $\alpha$ and $f$ )

HOW (naive, and why it's wrong): A first instinct is gated_clk = clk AND enable. This is dangerous because if enable changes while clk is high, you get a glitch (a runt pulse) that can falsely trigger flops.

Fix — the Integrated Clock Gating (ICG) cell: latch the enable on the low phase of the clock, so it is stable before the next high edge:

enable ──▶ [ Latch (transparent when clk=0) ] ──▶ en_latched
                                                    │
clk ─────────────────────────────────────────── AND ──▶ gated_clk

Because en_latched only updates while clk=0, the AND gate never sees a mid-cycle change during clk=1 → glitch-free.

WHAT it does NOT help: static leakage. The flops still sit powered; they just don't switch.

Technique 2: Power Gating (attacks $P_{static}$ )

HOW — the sleep transistor:

 Vdd ──[ Header PMOS ]── VVDD ── logic block ── VVSS ──[ Footer NMOS ]── GND
          ▲ sleep_b                                        ▲ sleep

VVDD is a virtual supply. When asleep, header off → VVDD floats down → block starves → leakage ≈ 0.

The costs (WHY it's not free):

Wake-up latency & rush current — restoring $V_{dd}$ recharges all the block's internal caps, drawing a big inrush spike.
State loss — flip-flops lose their contents. Fix with retention registers (a tiny always-on shadow latch keeps state).
Floating outputs — a sleeping block's outputs go undefined and can corrupt awake blocks. Fix with isolation cells that clamp outputs to a known value.
Area/IR-drop — the sleep FET is large and adds series resistance.

Break-even (WHY you don't gate for tiny idles): Power gating pays off only if energy saved during sleep exceeds wake-up energy: $P_{on}\cdot t_{idle} \;>\; E_{wakeup} \;\;\Rightarrow\;\; t_{idle} > t_{break-even}$

Figure — Low-power design techniques (clock - power gating)

Quick comparison

	Clock gating	Power gating
Targets	Dynamic power	Static (leakage) power
Mechanism	Stop the clock	Cut the supply
State kept?	Yes	No (need retention regs)
Wake latency	~1 cycle	Long (recharge)
Extra cells	ICG latch+AND	Sleep FET, isolation, retention

Worked Examples

Common Mistakes (Steel-manned)

Flashcards

Dynamic power formula and what each term means

P=\alpha C_L V_{dd}^2 f

;

\alpha

=activity factor,

C_L

=switched cap,

V_{dd}

=supply (squared),

f

=frequency.

Why does one full charge/discharge cycle dissipate

C_L V_{dd}^2

Supply delivers

Q V_{dd}=C_L V_{dd}^2

per charge; half burned charging, half discharging → total

C_L V_{dd}^2

per cycle.

What does clock gating reduce?

Dynamic switching power, by setting a register's local activity factor

\alpha

to ~0.

What does power gating reduce?

Static leakage power, by disconnecting the block from

V_{dd}

via a sleep transistor.

Why is clk AND enable a bad clock gate?

enable changing while clk=1 creates glitches/runt pulses that can falsely clock flops.

What is an ICG cell?

Integrated clock gating: a latch (transparent on clk low) feeding an AND, making enable stable during clk high → glitch-free.

What is a retention register?

A flip-flop with an always-on shadow latch that preserves state while the main block is power-gated.

Purpose of isolation cells?

Clamp a sleeping block's outputs to a known value so floating outputs don't corrupt awake logic.

Power-gating break-even condition

Gate only if

t_{idle} > E_{wakeup}/P_{on}

, else wake-up energy exceeds leakage saved.

Which term dominates dynamic-power reduction,

V_{dd}

f

V_{dd}

— it's squared, so scaling voltage helps more (but slows gates).

Header vs footer switch?

Header = PMOS between

V_{dd}

and virtual VDD; footer = NMOS between virtual VSS and GND.

Recall Feynman: explain to a 12-year-old

Imagine a big house full of lights and running taps. Clock gating is like turning off lights in rooms nobody is using — the room is still connected to electricity, but nothing flickers, so you save on the "flickering" bill. Power gating is like flipping the main breaker for the whole empty wing — now even the tiny bit of electricity that leaks through switched-off lights is gone. But when you flip that breaker back on, the lights take a moment to warm up and the clocks reset (you lose state) — so you only do it if the wing will be empty for a long time.

Connections

CMOS Inverter Power Dissipation
Dynamic Voltage and Frequency Scaling (DVFS)
Leakage Currents in Nanometer CMOS
Multi-Vth Design
Retention Flip-Flops and UPF Power Intent
Clock Tree Synthesis

Concept Map

Hinglish (regional understanding)

Intuition Hinglish mein samjho

Dekho, chip do tarike se power kha jaati hai. Pehla — dynamic power — jab transistors switch karte hain, capacitors charge/discharge hote hain, aur uska formula hai $P=\alpha C_L V_{dd}^2 f$ . Yahan $V_{dd}$ square me hai, matlab voltage kam karna sabse zyada faayda deta hai. Dusra — static/leakage power — jab transistor "off" bhi ho tab bhi thoda current leak karta hai, aur modern chips me yeh bohot bada issue hai.

Clock gating dynamic power ko maarta hai. Agar koi register apni value change hi nahi kar raha, phir bhi uska clock toggle hota rehta hai aur clock-tree buffers power khaate hain — bekaar me. To hum us register ka clock rok dete hain (enable signal se), jisse uska activity factor $\alpha$ zero ho jaata hai. Lekin seedha clk AND enable mat karo — glitch aa sakta hai. Isliye ICG cell use karte hain jo enable ko clock ke low phase me latch karta hai, taaki glitch-free rahe.

Power gating leakage ko maarta hai. Ek bada sleep transistor (header ya footer) lagate hain jo idle block ko supply se disconnect kar deta hai — leakage almost zero. Par cost hai: block ka state chala jaata hai (isliye retention registers chahiye), outputs float ho jaate hain (isliye isolation cells), aur wake-up me time aur rush current lagta hai. Isliye ek break-even hota hai: sirf tab gate karo jab block kaafi der idle rahega, warna wake-up ki energy leakage se zyada ho jaayegi.

Simple yaad rakho: CLOCK stops the TICK (dynamic bachaata hai), POWER pulls the PLUG (leakage bachaata hai). Dono alag problems solve karte hain, aur real chips me dono saath use hote hain.

Test yourself — VLSI Design

Connections