Low-power design techniques (clock - power gating)

4.2.15 · Hardware › VLSI Design

CMOS chip bilkul power kyon jalaati hai?

Kisi bhi technique se pehle, hume jaanna chahiye ki hum kisse lad rahe hain. Total power teen mein baanti hai:

$P_{t o t a l} = P_{d y nami c} + P_{s h or t} + P_{s t a t i c}$

Dynamic (switching) power — scratch se derive kiya hua

Derivation (WHY yeh famous formula sahi hai):

Cap par stored charge jab $V_{dd}$ tak charge hoti hai: $Q = C_{L} V_{dd}$

Ek charge ke dauran supply se li gayi energy ( $V_{dd}$ par rakha gaya supply): $E_{s u ppl y} = Q V_{dd} = C_{L} V_{dd}^{2}$

Uska aadha cap par stored hota hai ( $\frac{1}{2} C_{L} V_{dd}^{2}$ ), aadha pull-up resistance mein jal jaata hai. Agle discharge par, stored aadha pull-down mein jal jaata hai. Toh ek poora 0→1→0 cycle $C_{L} V_{dd}^{2}$ dissipate karta hai.

Agar node $f$ full cycles per second banata hai aur sirf $α$ probability ke saath switch karta hai (activity factor), tab:

$P_{d y nami c} = α C_{L} V_{dd}^{2} f$

Static (leakage) power

Ek transistor jo "off" hai woh bhi subthreshold current $I_{l e ak}$ leak karta hai: $P_{s t a t i c} = V_{dd} I_{l e ak}$ Yeh modern nodes mein dominate karta hai aur switching par depend nahi karta — ek idle block phir bhi leak karta hai. Isi wajah se hume power gating chahiye.

Technique 1: Clock Gating ( $α$ aur $f$ par attack karta hai)

HOW (naive approach, aur yeh galat kyon hai): Pehla instinct hai gated_clk = clk AND enable. Yeh dangerous hai kyunki agar enable tab change ho jab clk high ho, toh ek glitch (ek runt pulse) milti hai jo flops ko falsely trigger kar sakti hai.

Fix — Integrated Clock Gating (ICG) cell: enable ko clock ke low phase par latch karo, taaki yeh next high edge se pehle stable ho:

enable ──▶ [ Latch (transparent when clk=0) ] ──▶ en_latched
                                                    │
clk ─────────────────────────────────────────── AND ──▶ gated_clk

Kyunki en_latched sirf tab update hota hai jab clk=0 ho, AND gate ko clk=1 ke dauran mid-cycle change kabhi nahi dikti → glitch-free.

YEH KYA HELP NAHI KARTA: static leakage. Flops abhi bhi powered baithe hain; woh sirf switch nahi karte.

Technique 2: Power Gating ( $P_{s t a t i c}$ par attack karta hai)

HOW — sleep transistor:

 Vdd ──[ Header PMOS ]── VVDD ── logic block ── VVSS ──[ Footer NMOS ]── GND
          ▲ sleep_b                                        ▲ sleep

VVDD ek virtual supply hai. Jab asleep ho, header off → VVDD neeche float karta hai → block starve hota hai → leakage ≈ 0.

Costs (WHY yeh free nahi hai):

Wake-up latency aur rush current — $V_{dd}$ restore karne par block ke saare internal caps recharge hote hain, ek bada inrush spike draw karke.
State loss — flip-flops apna content kho dete hain. Fix karo retention registers se (ek tiny always-on shadow latch state preserve karta hai).
Floating outputs — ek sleeping block ke outputs undefined ho jaate hain aur awake blocks ko corrupt kar sakte hain. Fix karo isolation cells se jo outputs ko ek known value par clamp karti hain.
Area/IR-drop — sleep FET bada hota hai aur series resistance add karta hai.

Break-even (WHY tum choti idles ke liye gate nahi karte): Power gating tabhi faaydemand hoti hai jab sleep mein bachi energy wake-up energy se zyada ho: $P_{o n} \cdot t_{i d l e} > E_{w ak e u p} \Rightarrow t_{i d l e} > t_{b r e ak - e v e n}$

Figure — Low-power design techniques (clock - power gating)

Quick comparison

	Clock gating	Power gating
Targets	Dynamic power	Static (leakage) power
Mechanism	Clock rok do	Supply kaat do
State rahti hai?	Haan	Nahi (retention regs chahiye)
Wake latency	~1 cycle	Lamba (recharge)
Extra cells	ICG latch+AND	Sleep FET, isolation, retention

Worked Examples

Common Mistakes (Steel-manned)

Flashcards

Dynamic power formula aur har term ka matlab

P = α C_{L} V_{dd}^{2} f

;

α

=activity factor,

C_{L}

=switched cap,

V_{dd}

=supply (squared),

f

=frequency.

Ek full charge/discharge cycle

C_{L} V_{dd}^{2}

kyon dissipate karta hai?

Supply har charge par

Q V_{dd} = C_{L} V_{dd}^{2}

deliver karta hai; aadha charging mein jalta hai, aadha discharging mein → total

C_{L} V_{dd}^{2}

per cycle.

Clock gating kya reduce karta hai?

Dynamic switching power, ek register ka local activity factor

α

~0 set karke.

Power gating kya reduce karta hai?

Static leakage power, block ko sleep transistor ke zariye

V_{dd}

se disconnect karke.

clk AND enable ek bura clock gate kyon hai?

enable ka clk=1 ke dauran change hona glitches/runt pulses create karta hai jo flops ko falsely clock kar sakte hain.

ICG cell kya hota hai?

Integrated clock gating: ek latch (clk low par transparent) jo ek AND ko feed karta hai, enable ko clk high ke dauran stable banata hai → glitch-free.

Retention register kya hota hai?

Ek flip-flop jisme ek always-on shadow latch hota hai jo state preserve karta hai jab main block power-gated ho.

Isolation cells ka purpose?

Ek sleeping block ke outputs ko ek known value par clamp karna taaki floating outputs awake logic ko corrupt na karein.

Power-gating break-even condition

Gate karo sirf agar

t_{i d l e} > E_{w ak e u p} / P_{o n}

ho, warna wake-up energy saved leakage se zyada ho jaati hai.

Dynamic-power reduction mein kaun zyada dominant hai,

V_{dd}

f

V_{dd}

— yeh squared hai, toh voltage scale karna zyada help karta hai (lekin gates slow ho jaate hain).

Header vs footer switch?

Header = PMOS

V_{dd}

aur virtual VDD ke beech; footer = NMOS virtual VSS aur GND ke beech.

Recall Feynman: ek 12-saal ke bachche ko explain karo

Ek bade ghar ki kalpana karo jisme bahut saari lights aur chalte naale hain. Clock gating aise hai jaise un rooms ki lights band karna jisme koi nahi hai — room abhi bhi electricity se connected hai, lekin kuch flicker nahi karta, toh tum "flickering" bill par bachate ho. Power gating aise hai jaise poori khaali wing ka main breaker flip karna — ab switched-off lights se jo thodi si electricity leak hoti thi woh bhi chali gayi. Lekin jab tum woh breaker wapas on karte ho, lights warm up hone mein thoda time lagta hai aur clocks reset ho jaate hain (state kho jaati hai) — toh tum yeh sirf tab karte ho jab wing lambe time ke liye khaali ho.

Connections

CMOS Inverter Power Dissipation
Dynamic Voltage and Frequency Scaling (DVFS)
Leakage Currents in Nanometer CMOS
Multi-Vth Design
Retention Flip-Flops and UPF Power Intent
Clock Tree Synthesis