Moore's Law and scaling trends: Exercises — Hardware deep dive

This page is a self-test. Each problem states cleanly what to find. Solutions are hidden inside collapsible callouts — try first, then reveal. Problems climb five levels:

Everything here builds on the parent topic. The core tool is the growth law $N (t) = N_{0} 2^{(t - t_{0}) / T_{d}},$ where $N_{0}$ is the transistor count at a starting year $t_{0}$ , $t$ is the year you ask about, and $T_{d}$ is the doubling time (how many years pass per ×2). We'll use it constantly.

Level 1 — Recognition

Recall Solution — L1.1

$N (t) = N_{0} 2^{(t - t_{0}) / T_{d}}$

$N (t)$ = transistor count at year $t$ .
$N_{0}$ = count at the starting year $t_{0}$ .
$t - t_{0}$ = years elapsed.
$T_{d}$ = doubling time ( $\approx 2$ years for Moore's Law). The exponent $(t - t_{0}) / T_{d}$ literally counts how many doublings have fit into the elapsed time; base $2$ performs each doubling.

Recall Solution — L1.2

False. It is an empirical, economic/industry observation — the industry invests to keep it true. Nothing in physics forces the doubling.

Recall Solution — L1.3

Dennard scaling. Moore's Law is only about count. Dennard is the device-physics engine giving faster switching and constant power density.

Level 2 — Application

Recall Solution — L2.1

Elapsed $= 2028 - 2018 = 10$ years $\Rightarrow$ doublings $= 10/2 = 5$ . $N = 5 \times 1 0^{8} \cdot 2^{5} = 5 \times 1 0^{8} \cdot 32 = 1.6 \times 1 0^{10} .$ Why: 5 doublings means × $2^{5} = 32$ .

Recall Solution — L2.2

The count grew by a factor $1 0^{3}$ over $22$ years. We need to solve $2^{22/ T_{d}} = 1 0^{3}$ . Why take a log? The unknown $T_{d}$ is trapped inside the exponent. Taking $lo g_{10}$ pulls it down where we can isolate it: $\frac{22}{T _{d}} lo g_{10} 2 = 3 \Rightarrow T_{d} = \frac{22 \times 0.301}{3} \approx 2.2 years.$ Matches Moore's ~2-year figure. ✔

Recall Solution — L2.3

Delay scales as $τ \propto 1/ κ = 1/ 2 \approx 0.707$ . Why: $τ = C V / I$ , and under Dennard $C \to 1/ κ$ , $V \to 1/ κ$ , $I \to 1/ κ$ , so $τ \propto \frac{( 1/ κ ) ( 1/ κ )}{1/ κ} = \frac{1}{κ} .$ Frequency $f = 1/ τ$ rises by $κ = 2 \approx 1.41 \times$ — ~41% faster per node.

Level 3 — Analysis

Recall Solution — L3.1

Taking $lo g_{10}$ of the growth law: $lo g_{10} N = lo g_{10} N_{0} + \frac{l o g _{10} 2}{T _{d}} (t - t_{0}) .$ This is a straight line in $t$ with slope $\frac{lo g _{10} 2}{T _{d}}$ . See the figure: both lines leave the same point but the $T_{d} = 2$ line is steeper.

Slope ratio: $\frac{slope _{T_{d} = 2}}{slope _{T_{d} = 3}} = \frac{1/2}{1/3} = \frac{3}{2} = 1.5.$ The faster-doubling company's line is 1.5× steeper — exponential speed becomes a simple slope on a log axis.

Recall Solution — L3.2

With $C \to 1/ κ$ and $V \to 1/ κ$ : $P \propto C V^{2} \to \frac{1}{κ} \cdot \frac{1}{κ ^{2}} = \frac{1}{κ ^{3}} (dynamic, ignoring f) .$ Including $τ \to 1/ κ$ so $f \to κ$ : $P \propto C V^{2} f \to \frac{1}{κ} \cdot \frac{1}{κ ^{2}} \cdot κ = \frac{1}{κ ^{2}}$ . Area $A \to 1/ κ^{2}$ . Therefore $\frac{P}{A} \to \frac{1/ κ ^{2}}{1/ κ ^{2}} = 1 (constant).$ The load-bearing assumption: ==voltage $V$ scales down with $κ$ == (see Dynamic Power CV2f). If $V$ freezes, the $V^{2}$ term stops shrinking and $P / A$ rises — that's the power wall.

Recall Solution — L3.3

Per transistor: $P \propto C V^{2} f$ . With $V, f$ fixed and $C \to 1/ κ$ : $P \to 1/ κ$ . Density $P / A$ : transistors per area rise by $κ^{2}$ , so $\frac{P}{A} \to \frac{( 1/ κ )}{( 1/ κ ^{2} )} = κ = 2 \approx 1.41.$ Power density rises ~41% per node — chips run hotter each generation. This is exactly the Dennard breakdown that pushed the industry toward Multi-core Architecture.

Level 4 — Synthesis

Recall Solution — L4.1

2005→2015 = 10 years = 5 nodes. Each node multiplies frequency by $κ = 2$ : $f_{2015} = 3 GHz \times (2)^{5} = 3 \times 2^{2.5} = 3 \times 5.657 \approx 16.97 GHz .$ Reality: clocks plateaued at ~3–4 GHz (the power wall). The doubling transistors — still delivered by Moore's Law — were spent on more cores (Multi-core Architecture), not more GHz. Ideal Dennard would have given ~17 GHz single cores; leakage-driven heat forbade it.

Recall Solution — L4.2

$300 mV = 3 S = 3$ decades. Each decade is ×10, so $\frac{I _{leak,new}}{I _{leak,old}} = 1 0^{300/100} = 1 0^{3} = 1000.$ Leakage explodes 1000× — see Leakage Current and Subthreshold Conduction. This is why $V_{t h}$ (and hence $V$ ) can't keep shrinking, which is the root cause of Dennard's death.

Recall Solution — L4.3

Power (dynamic $\propto$ active-transistor-count $\times f$ ; same total transistors):

A: $\propto N \cdot f$ .
B: 4 cores of $N /4$ each at $f /2$ : $\propto 4 \cdot (N /4) \cdot (f /2) = N f /2$ . B uses half the dynamic power. Throughput (ops/s $\propto$ cores × freq):
A: $1 \cdot f = f$ .
B: $4 \cdot (f /2) = 2 f$ . B is 2× throughput at half the power — the whole reason Multi-core Architecture won after Dennard ended. Lowering frequency drops the $C V^{2} f$ dynamic cost per core (see Dynamic Power CV2f) while parallelism recovers total work.

Level 5 — Mastery

Recall Solution — L5.1

At $t = t_{0}$ : exponent $= (t_{0} - t_{0}) / T_{d} = 0$ , and $2^{0} = 1$ , so $N (t_{0}) = N_{0} \cdot 1 = N_{0} .$ No degeneracy — it correctly returns the starting count. The formula is well-defined for all real $t$ : for $t < t_{0}$ the exponent is negative and $N < N_{0}$ (fewer transistors in the past), which is the correct backward extrapolation.

Recall Solution — L5.2

Atomic granularity: a channel can't be thinner than a few atoms; gate control over the channel collapses. This is why geometry shifted to FinFETs and gate-all-around, wrapping the gate to keep control.
Quantum tunnelling / leakage: as the gate oxide and channel thin, electrons tunnel through barriers — leakage rises exponentially and static power dominates. So even a perfectly funded Moore's Law hits hard physical walls; scaling is ultimately bounded by atoms and quantum mechanics, not just budgets.

Recall Solution — L5.3

Flawed premise: that the node name is a real physical length. Since ~2010 the node label ("3 nm", "5 nm") is a marketing name; no single feature is literally that size — gate lengths and pitches are considerably larger. So the "3 nm from the atomic limit" arithmetic is meaningless. Correct view: density improvements now come from structure (FinFET → GAA → 3D stacking, FinFET and Gate-All-Around) and design, not just shrinking one length. Moore's Law (transistor count) has continued past the point the naive-name arithmetic would forbid — because the name never was the length.

Recall Solution — L5.4

Per transistor: $P \propto C V^{2} f$ . With $V, f$ fixed and $C \to 1/ κ$ : each transistor's power $\to 1/ κ$ . But transistor count $\to 2$ (double per node). Total: $P_{total} \to 2 \times \frac{1}{κ} = \frac{2}{2} = 2 \approx 1.41.$ Total power would rise ~41% per node if all transistors ran at once. Since the cooling budget is fixed, you cannot power them all — hence dark silicon: a growing fraction of the chip must stay switched off ("dark") at any instant.

Recall One-line summary of the whole page

The growth law $N = N_{0} 2^{(t - t_{0}) / T_{d}}$ becomes a straight line on a log axis (L1–L3); Dennard kept power density flat only while $V$ shrank (L3); once $V$ and $f$ froze, extra transistors meant more heat/cores/dark silicon, not more GHz (L4–L5); and the ultimate limit is atoms + tunnelling, not budgets (L5).