Moore's Law and scaling trends — Hinglish notes

4.2.1 · Hardware › VLSI Design

Moore's Law KYA hai?

YEH physical law KYU nahi hai: Physics mein kuch bhi doubling ko force nahi karta. Yeh ek self-fulfilling economic/industry roadmap hai — semiconductor industry ne targets aur R&D budgets set kiye taaki trend chalti rahe. Yeh engineering effort ki wajah se hold karta hai, natural necessity ki wajah se nahi.

KON SI quantity actually double hoti hai: transistor count per chip — minimum feature size ("node", jaise 7 nm, 5 nm, 3 nm) ko shrink karke.

Exponential KAISE kaam karta hai — derive karo

Hum chahte hain transistor count vs. time ka ek formula. Rule se shuru karo: har $T_{d}$ saal mein 2 se multiply karo (doubling time).

Maano $N_{0}$ = year $t_{0}$ par transistors, aur $t$ = current year.

Kitni doublings ho chuki hain: $n = \frac{t - t _{0}}{T _{d}}$

Har doubling 2 se multiply karti hai, toh $n$ doublings ke baad: $N (t) = N_{0} \cdot 2^{(t - t_{0}) / T_{d}}$

Log plot par linear kyun dikhta hai: $lo g_{10}$ lo: $lo g_{10} N (t) = lo g_{10} N_{0} + \frac{t - t _{0}}{T _{d}} lo g_{10} 2$ Yeh $t$ mein ek straight line hai jiska slope $\frac{l o g _{10} 2}{T _{d}}$ hai. Isliye Moore's Law hamesha semi-log graph par draw ki jaati hai — exponential ek diagonal line ban jaata hai.

Dennard Scaling — Chhota KYU better bhi tha (sirf zyada nahi)

Moore's Law kehti hai "zyada transistors." Dennard scaling (1974) explain karta hai kyun woh chhote transistors faster aur cooler bhi the. Yeh scaling ke golden age ka physics engine hai.

Setup: Har dimension (length $L$ , width $W$ , oxide thickness $t_{o x}$ ) aur voltage $V$ ko same factor $κ > 1$ se scale down karo (jaise $κ = 1.4 = 2$ per node — har node par area half hota hai).

Device physics se consequences derive karo:

Quantity	Relation	Scales as
Area	$A = L \cdot W$	$1/ κ^{2}$
Gate capacitance	$C = ε \frac{W L}{t _{o x}}$	$1/ κ$
Voltage	$V$	$1/ κ$
Current	$I \propto \frac{W}{L} (V)^{2}$ -ish, $\to$	$1/ κ$
Gate delay	$τ = \frac{C V}{I}$	$1/ κ$ (faster!)
Power/transistor	$P = \frac{1}{2} C V^{2} f, \propto C V^{2}$	$1/ κ^{2}$
Power density	$P / A = \frac{P}{A}$	$\frac{1/ κ ^{2}}{1/ κ ^{2}} = 1$ constant!

Gate delay ki derivation (Kyun $τ \propto 1/ κ$ ): $τ = \frac{C V}{I} = \frac{( 1/ κ ) ( 1/ κ )}{( 1/ κ )} = \frac{1}{κ}$ Delay shrink hoti hai → clock frequency badhti hai. Isliye 1990s mein CPU clocks tezi se upar gayi.

YEH KYUN TUTA — Dennard scaling ka ant (~2005)

Agar $V$ = constant jab transistors double hote rahe: $\frac{P}{A} \propto \frac{C V ^{2} f}{A} ↑ (power density ab har node par BADHTI hai)$ Yeh hai Power Wall → chips pighal jaati. Industry ka response: clock frequency badhana band karo, instead multi-core jao. (Wahi transistor budget speed ki jagah parallelism par kharch karo.)

Moore's Law (transistor count) jaari rahi FinFETs, GAA, 3D stacking ke zariye — lekin Dennard scaling khatam ho gayi, isliye single-thread speed stall ho gayi.

Worked Examples

Common Mistakes

Recall Feynman: 12-saal ke bachche ko samjhao

Socho LEGO bricks jo har kuch saalon mein aadhi width ki ho jaati hain. Achanak tum usi box mein do guni bricks fit kar sakte ho! Matlab tum har 2 saal mein bina bade box ke ek bahut cool LEGO castle bana sakte ho. Kafi time tak woh chhoti bricks faster snap bhi karti thi aur cool bhi rehti thi. Lekin aakhirkar bricks ITNI chhoti ho gayi ki woh heat leak karne lagi aur aur zyada squeeze karne par aag lag jaati — toh ek super-fast castle banane ki jagah, builders ab kai castles side by side banate hain (yahi "multi-core" hai).

Active Recall

Moore's Law kya kehta hai?

Economically optimal chip par transistor count ~har 2 saal mein double hoti hai (empirical observation, physical law nahi).

Transistor-growth formula kya hai?

N (t) = N_{0} 2^{(t - t_{0}) / T_{d}}

jahan

T_{d} \approx 2

years.

Moore's Law semi-log axis par kyun plot hota hai?

Kyunki

lo g N

time mein linear hai, toh exponential growth ek straight line dikhti hai.

Dennard scaling kya describe karta hai (vs Moore's Law)?

Kaise transistors ko chhota karna unhe faster aur lower-power banata hai, power density constant rakhta hai — yeh physics hai jo explain karta hai kyun zyada transistors better bhi the.

Dennard scaling mein gate delay kaise scale hoti hai?

τ = C V / I \propto 1/ κ

— chhota = faster.

Ideal Dennard scaling mein power density kaise scale hoti hai?

Constant (

P / A

~fixed rehta hai).

Dennard scaling kab aur kyun khatam hui?

~2005; voltage ~1 V se neeche scale nahi ho sakta tha bina leakage current ke explode hue, toh power density badhne lagi (power wall).

Power wall ke jawab mein industry ne kya kiya?

Clock frequency badhana band kiya; multi-core gaye (speed ki jagah parallelism).

"Dark silicon" kya hai?

Chip ke woh hisse jo powered off rehne chahiye kyunki tum thermal budget ke andar saare transistors simultaneously power nahi kar sakte.

Kya "5 nm" aaj ek real physical feature size hai?

Nahi — yeh ek marketing/node label hai, literally measured length nahi.

Agar ek design node factor

κ = 2

se shrink ho, toh area ka kya hoga?

Half ho jaata hai (

1/ κ^{2} = 1/2

), density double ho jaati hai.

Connections

VLSI Design — parent chapter
Dennard Scaling — Moore era speedups ka physics engine
CMOS Transistor — woh device jo scale ho raha hai
Dynamic Power CV2f — derivation mein use ki gayi power equation
Leakage Current and Subthreshold Conduction — kyun voltage scaling ruk gayi
Multi-core Architecture — power wall ka industry answer
FinFET and Gate-All-Around — planar CMOS ke baad count-scaling kaise jaari rahi