3D stacking and through-silicon vias (TSV)

WHAT is being solved?

HOW a TSV is built (derivation from physics, not magic)

Etch a deep narrow hole (via) using Deep Reactive-Ion Etching (DRIE / Bosch process) — alternating etch + passivation gives near-vertical walls.
Line the wall with an insulating oxide (silicon is semiconducting; without this the via shorts to the substrate) + a barrier (e.g. TaN, stops copper diffusing into silicon which would poison transistors).
Fill with copper by electroplating.
Thin the wafer from the back (grind down to tens of µm) so the via now pokes out the bottom → "via reveal."
Bond to the next die with microbumps or hybrid Cu–Cu bonding.

Formula The insulated TSV is a coaxial capacitor

WHY derive this: A TSV isn't a perfect wire — it has capacitance to the silicon around it, and that capacitance is a load that slows signals and burns energy. Model it as a coax: copper core (radius $a$ ), oxide liner (out to radius $b$ ), grounded silicon outside.

Gauss's law for a line charge $\lambda$ through cylindrical oxide (permittivity $\varepsilon$ ): $E(r) = \frac{\lambda}{2\pi \varepsilon r}$ Voltage between core and silicon over via length $h$ (charge $Q=\lambda h$ ): $V = \int_a^b E\,dr = \frac{\lambda}{2\pi\varepsilon}\ln\frac{b}{a}$ Capacitance $C=Q/V=\lambda h/V$ : $\boxed{C_{\text{TSV}} = \frac{2\pi \varepsilon\, h}{\ln(b/a)}}$ Read it: thicker oxide (bigger $b$ ) → smaller $C$ → faster, lower energy. Longer via ( $h$ ) → bigger $C$ . This is why we thin the wafer — it directly shrinks $h$ .

Formula Vertical RC delay beats horizontal — the whole point

Signal energy per switch is $E=\tfrac12 C V^2$ and delay scales with $RC$ . For a wire, $R\propto \ell$ and $C\propto \ell$ , so $\tau_{\text{wire}} \propto RC \propto \ell^2.$ A horizontal cross-chip route $\ell_{2D}\sim$ mm; a TSV $\ell_{3D}=h\sim$ 50 µm. Ratio of delays: $\frac{\tau_{3D}}{\tau_{2D}} \sim \left(\frac{h}{\ell_{2D}}\right)^2 = \left(\frac{50\,\mu m}{5000\,\mu m}\right)^2 = 10^{-4}.$ The vertical path is orders of magnitude cheaper. That's the physics that pays for all the manufacturing pain.

Figure — 3D stacking and through-silicon vias (TSV)

Bandwidth: why area beats perimeter

Worked examples

Worked example 1 — TSV capacitance

Copper core radius $a=2.5\,\mu m$ , oxide out to $b=3\,\mu m$ , height $h=50\,\mu m$ , oxide $\varepsilon_r=3.9$ , $\varepsilon_0=8.85\times10^{-12}$ F/m. Step 1: $\varepsilon=3.9\times8.85\times10^{-12}=3.45\times10^{-11}$ F/m. Why? Absolute permittivity of the liner. Step 2: $\ln(b/a)=\ln(1.2)=0.182$ . Why? The log geometry factor from the coax derivation. Step 3: $C=\dfrac{2\pi(3.45\times10^{-11})(50\times10^{-6})}{0.182}=5.96\times10^{-14}$ F $\approx 60$ fF. Why? Plug into $C=2\pi\varepsilon h/\ln(b/a)$ . Real TSVs are tens of fF — matches.

The catch: heat (steel-man of "just stack more")

Flashcards

What does TSV stand for and what does it physically do?

Through-Silicon Via — a metal-filled vertical tunnel through a silicon die connecting it to a stacked die above/below.

Why must a TSV have an oxide liner?

Silicon is semiconducting; without insulation the copper would short to the substrate (and copper would diffuse in and poison transistors → also needs a barrier).

Give the TSV capacitance formula and its coax analogy.

C=\dfrac{2\pi\varepsilon h}{\ln(b/a)}

; core=copper radius

a

, oxide to

b

, grounded silicon outside — a coaxial capacitor.

Why do we thin the wafer during 3D integration?

It shortens the via length

h

, which lowers

C_{TSV}

(faster, lower-energy) and reveals the via bottom for bonding.

Why does 3D stacking give more bandwidth than 2D?

2D I/O leaves through the edge (∝ L, perimeter); 3D I/O uses the whole face (∝ L², area) → far more parallel links (basis of HBM's wide bus).

Why does wire delay scale as length²?

Both R and C of a wire scale with length, and delay ∝ RC ∝ length².

What is the #1 limiter of 3D stacking?

Heat/thermal density — power multiplies in a fixed footprint but buried layers can't dump heat easily.

Difference between 2.5D and 3D integration?

2.5D: dies side-by-side on an interposer (TSVs in interposer). 3D: dies stacked directly, TSVs through the active dies.

What is a keep-out zone (KOZ)?

Area around a TSV where no transistors are placed, because TSV thermo-mechanical stress degrades device performance.

Name the etch process used to drill TSVs.

Deep Reactive-Ion Etching (DRIE / Bosch process) for near-vertical high-aspect-ratio holes.

Recall Feynman: explain to a 12-year-old

Imagine a city where every house is on one flat street. To send a letter to a friend it has to travel far across town — slow and tiring. Now imagine building the houses as a tall apartment block: your friend lives on the floor right above you, so you just poke a tiny pipe through the ceiling and drop the letter — instant! A TSV is that pipe through the floor/ceiling, and 3D stacking is stacking the chips like apartment floors. The only problem: pack too many hot floors together and the middle apartments get too hot, so you can't stack forever.

Connections

Moore's Law — 3D is a "More-than-Moore" scaling path when transistor shrink slows.
High Bandwidth Memory (HBM) — the flagship product of TSV stacking.
Interposers and 2.5D Integration — the sibling technology.
Interconnect RC Delay — the physics motivating vertical wires.
Chiplets and Heterogeneous Integration — how stacking mixes process nodes.
Thermal Management in ICs — the constraint that caps stacking.
Chip Packaging — microbumps, hybrid bonding, wafer thinning.

Concept Map

Hinglish (regional understanding)

Intuition Hinglish mein samjho

Dekho, purane zamane mein hum chip ko sirf flat, ek hi floor pe banate the — sab transistor aur wires ek hi plane pe faile hue. Problem ye thi ki data ko ek kone se dusre kone tak jaana padta tha, aur ye horizontal safar slow aur energy-hungry hota gaya. 3D stacking ka idea simple hai: chip ko ek building ki tarah upar ki taraf banao, floor pe floor. Ab data ko door tak jaane ki zaroorat nahi — bas upar wale floor pe seedha jump.

Us "jump" ke liye chahiye ek lift shaft — wahi hai TSV (Through-Silicon Via). Ye ek metal (copper) se bhara vertical tunnel hai jo poora silicon die ke aar-paar chalta hai. Kyunki silicon thoda conductive hota hai, TSV ke around ek oxide liner dalna padta hai warna short circuit ho jaayega. Formula $C=\frac{2\pi\varepsilon h}{\ln(b/a)}$ ek coaxial capacitor jaisa hai — isse pata chalta hai ki agar via chhota (wafer thinning) aur oxide thoda mota ho, to capacitance kam, matlab fast aur low-energy.

Ye kyun important hai? Do baaton se: (1) Speed & energy — vertical hop mm ke bajaye 50 micron ka hota hai, aur wire delay length ke square se badhta hai, to bahut bada faayda. (2) Bandwidth — 2D chip sirf apne kinaron (edge) se baat karta hai, par stacked chip poore face se, isliye hazaaron parallel connections milte hain. Yahi HBM memory ka raaz hai — 1024-bit wide bus, TB/s bandwidth.

Lekin ek catch hai: garmi (heat). Jab tum saari power ek hi chhote footprint mein pack karte ho, beech wale floors garam ho jaate hain aur unhe cool karna mushkil hota hai. Isiliye zyada tar hum ek hot logic die ke upar thandi memory rakhte hain, poori logic-on-logic building banana risky hota hai. Yaad rakho: short wires, wide bus, par hot stack.

WHAT is being solved?

HOW a TSV is built (derivation from physics, not magic)

Bandwidth: why area beats perimeter

Worked examples

The catch: heat (steel-man of "just stack more")

Flashcards

Connections

Concept Map

Hinglish (regional understanding)

Go deeper — visual, from zero

Test yourself — Advanced & Emerging Architectures

Connections