Level 1 — RecognitionAdvanced & Emerging Architectures

Advanced & Emerging Architectures

⏱ 20 minutes40 marksprintable — key stays hidden on paper

Chapter: 6.5 Advanced & Emerging Architectures Level: 1 — Recognition (MCQ, Matching, True/False with justification) Time limit: 20 minutes Total marks: 40

Section A — Multiple Choice (1 mark each, 12 marks)

Choose the single best answer.

Q1. A "chiplet" refers to:

A) A software module for accelerators
B) A small, separately fabricated die integrated with others into one package
C) A cooling component in 3D stacks
D) A photonic waveguide segment

Q2. The primary role of a silicon interposer in 2.5D packaging is to:

A) Provide vertical stacking of DRAM
B) Act as a passive substrate routing fine-pitch interconnects between dies
C) Replace the processor core logic
D) Store cache data

Q3. Through-Silicon Vias (TSVs) are used primarily in:

A) 2D planar routing only
B) 3D die stacking for vertical electrical connections
C) Optical interconnects
D) FPGA lookup tables

Q4. High Bandwidth Memory (HBM) achieves its high bandwidth mainly by:

A) Using very high clock frequencies on a narrow bus
B) A very wide I/O bus across stacked DRAM dies connected via TSVs
C) Optical links between DRAM chips
D) Storing data in SRAM cells

Q5. The core computational structure of a Google TPU is a:

A) Out-of-order superscalar pipeline
B) Systolic array of multiply-accumulate units
C) Ring of GPU shaders
D) Content-addressable memory

Q6. Processing-in-Memory (PIM) primarily aims to reduce:

A) Transistor count
B) Data-movement energy/latency between memory and compute
C) Clock jitter
D) Photon loss

Q7. A key advantage of FPGA-based acceleration over ASICs is:

A) Lower unit cost at very high volume
B) Reconfigurability / faster time-to-deployment
C) Always higher clock speed
D) No need for HDL

Q8. In quantum computing hardware, the basic unit of information is the:

A) Bit
B) Qubit
C) Trit
D) Byte

Q9. Neuromorphic computing is characterized by:

A) Dense floating-point matrix units
B) Spiking, event-driven neuron/synapse models
C) Optical amplifiers only
D) Ternary content memory

Q10. RISC-V is attractive for custom accelerators mainly because it:

A) Is a closed proprietary ISA
B) Has an open ISA allowing custom instruction extensions
C) Requires no compiler support
D) Only runs on FPGAs

Q11. Approximate computing improves efficiency by:

A) Always increasing precision
B) Trading small accuracy loss for lower energy/latency
C) Using more transistors per operation
D) Removing all arithmetic units

Q12. A wafer-scale engine (Cerebras-style) is distinctive because it:

A) Uses many small packaged chips on a board
B) Builds one enormous processor from an (almost) entire wafer without dicing into small dies
C) Is purely a memory device
D) Relies only on photonic compute

Section B — Matching (1 mark each, 10 marks)

Match each term (Q13–Q22) to the best description (i–x).

#	Term
Q13	Co-packaged optics
Q14	OpenTitan
Q15	Dataflow architecture
Q16	NPU
Q17	2.5D packaging
Q18	HBM3
Q19	Domain-specific accelerator
Q20	Photonic interconnect
Q21	Systolic array
Q22	3D stacking

Descriptions:

(i) Optical engines placed in the same package as the switch/ASIC to cut link power
(ii) An open-source silicon root-of-trust project
(iii) Execution driven by availability of operands rather than a program counter
(iv) Accelerator specialized for neural-network inference/training on devices
(v) Dies placed side-by-side on an interposer
(vi) Latest-generation stacked DRAM with higher per-stack bandwidth
(vii) Hardware tailored to one class of workloads for efficiency
(viii) Data transmission using light instead of electrical signals
(ix) Grid of MACs passing partial results rhythmically between neighbors
(x) Vertically integrated dies connected by TSVs

Section C — True/False with Justification (2 marks each, 18 marks)

State True or False (1 mark) and give a one-line justification (1 mark).

Q23. TSVs allow vertical connections and shorter interconnect distances than routing all signals off-chip.

Q24. HBM uses a narrow, extremely high-frequency serial bus, unlike GDDR.

Q25. A systolic array reuses each loaded operand across many MAC operations, reducing memory bandwidth demand.

Q26. Chiplets improve manufacturing yield because smaller dies have fewer defects per die.

Q27. In dataflow architectures, an instruction executes as soon as its input operands are ready.

Q28. Neuromorphic chips are best suited for high-precision scientific double-precision computation.

Q29. Approximate computing is acceptable for exact financial ledger arithmetic.

Q30. Co-packaged optics reduce the electrical trace length between the switch ASIC and the optical transceiver.

Q31. RISC-V custom extensions require licensing fees from a central authority before use.

Answer keyMark scheme & solutions

Section A (1 mark each)

Q	Ans	Why
Q1	B	Chiplet = small separately fabricated die combined in one package.
Q2	B	Interposer is a passive layer providing fine-pitch die-to-die routing.
Q3	B	TSVs give vertical electrical paths through the silicon in 3D stacks.
Q4	B	HBM bandwidth comes from a very wide (1024-bit class) bus over stacked dies via TSVs, at moderate clocks.
Q5	B	TPU multiplies matrices in a systolic MAC array.
Q6	B	PIM moves compute near/into memory to cut data-movement cost.
Q7	B	FPGAs are reconfigurable, enabling fast deployment/updates.
Q8	B	Qubit is the quantum unit of information.
Q9	B	Neuromorphic = spiking, event-driven neuron/synapse computation.
Q10	B	Open ISA permits custom instruction extensions.
Q11	B	Trades small accuracy loss for energy/latency savings.
Q12	B	Wafer-scale engine keeps the wafer intact as one huge processor.

Section B (1 mark each)

Q	Match
Q13 Co-packaged optics	(i)
Q14 OpenTitan	(ii)
Q15 Dataflow architecture	(iii)
Q16 NPU	(iv)
Q17 2.5D packaging	(v)
Q18 HBM3	(vi)
Q19 Domain-specific accelerator	(vii)
Q20 Photonic interconnect	(viii)
Q21 Systolic array	(ix)
Q22 3D stacking	(x)

Section C (2 marks each: 1 verdict + 1 justification)

Q23. True. TSVs replace long off-chip paths with short vertical links → lower latency/energy.

Q24. False. HBM uses a wide parallel bus (many I/Os) at moderate clock; GDDR uses the narrower high-frequency approach.

Q25. True. Operands stream/stay stationary and are reused across neighboring MACs, so off-chip bandwidth per op drops.

Q26. True. Defect density is roughly constant per area; smaller dies have lower probability of containing a defect → higher yield per die.

Q27. True. Dataflow execution is triggered by operand availability, not a program counter.

Q28. False. Neuromorphic hardware targets low-precision, event-driven, sparse workloads, not high-precision FP64.

Q29. False. Financial ledgers need exact arithmetic; approximation would corrupt results.

Q30. True. Co-packaging places optics next to the ASIC, shortening lossy electrical traces and saving SerDes power.

Q31. False. RISC-V is open; custom extensions can be implemented without paying a central licensing fee.

Yield illustration (supports Q26)

If defect density $D = 0.5/\text{cm}^2$ , a Poisson yield model $Y = e^{-A D}$ gives higher yield for smaller area $A$ . For $A=1\,\text{cm}^2$ : $Y=e^{-0.5}\approx0.607$ ; for $A=4\,\text{cm}^2$ : $Y=e^{-2}\approx0.135$ . Smaller die ⇒ higher yield.

[
  {"claim":"Small die (1 cm^2) has higher Poisson yield than large die (4 cm^2) at D=0.5",
   "code":"from sympy import exp\nD=0.5\nY_small=exp(-1*D)\nY_large=exp(-4*D)\nresult = bool(Y_small > Y_large)"},
  {"claim":"Yield for A=1cm^2, D=0.5 approx 0.6065",
   "code":"from sympy import exp, Abs\nY=exp(-0.5)\nresult = bool(Abs(float(Y)-0.6065) < 0.001)"},
  {"claim":"HBM wide-bus example: 1024-bit bus at 3.2 Gbps/pin exceeds narrow 32-bit at 16 Gbps/pin in bytes/s",
   "code":"hbm=1024*3.2e9\ngddr=32*16e9\nresult = bool(hbm > gddr)"}
]