3D stacking and through-silicon vias (TSV): Worked examples

Before any symbol appears, let's re-earn them in plain words so a newcomer can start at line one.

Definition The symbols we will use (each anchored to a picture)

Picture a copper straw stuck straight down through a slice of silicon.

$a$ ::= the radius of the copper core (the metal filling), in metres. It is the inner circle of the straw.
$b$ ::= the radius out to the outer edge of the oxide liner, the thin glass sleeve around the copper. So $b > a$ always.
$h$ ::= the height (length) of the via, i.e. how thick the silicon slice is. This is the vertical drop.
$ε$ ::= the permittivity of the oxide — a material number saying "how much charge this insulator soaks up per volt." We write $ε = ε_{r} ε_{0}$ , where $ε_{0} = 8.85 \times 1 0^{- 12}$ F/m is the vacuum value and $ε_{r}$ (a pure number) is how many times worse than vacuum.
$C$ ::= the capacitance in farads (F). One farad = one coulomb of charge stored per volt. TSVs land in femtofarads, $1 fF = 1 0^{- 15}$ F.
$V$ ::= the signalling voltage (volts) — the height of a logic "1".
$L$ ::= the side length of a square die; $p$ ::= the pitch, the centre-to-centre spacing of connection pads.

Look at the figure: the copper core (blue), the pale oxide ring (yellow) out to $b$ , and the grey silicon that the outside voltage is measured against. Every formula below reads off this one cross-section.

The scenario matrix

Here is every case class this topic can throw at you. Each row is a "cell"; the last column names the example that lands on it.

#	Case class	What is being pushed	Example
A	Baseline capacitance	ordinary $a, b, h$	Ex 1
B	Degenerate: thin oxide $b \to a$	$ln (b / a) \to 0$ , limiting behaviour	Ex 2
C	Degenerate: zero length $h \to 0$	$C \to 0$ (the thinning limit)	Ex 3
D	Energy from capacitance	apply $E = \frac{1}{2} C V^{2}$ , compare 2D/3D	Ex 4
E	Sign / direction of change	which knob helps? sensitivity	Ex 5
F	I/O counting, edge vs area	$N_{2 D}$ vs $N_{3 D}$ , crossover	Ex 6
G	Real-world word problem	HBM bandwidth end-to-end	Ex 7
H	Thermal limiting case	Fourier $Δ T$ , the ceiling	Ex 8
I	Exam twist	back-solve for oxide thickness	Ex 9

We now walk them in order. Every numeric answer is machine-checked at the bottom.

Cell A — Baseline capacitance

Worked example Ex 1 — a normal TSV

Copper core $a = 2.5 μ m$ , oxide out to $b = 3 μ m$ , height $h = 50 μ m$ , oxide $ε_{r} = 3.9$ . Forecast: guess the answer first — will it be picofarads (10⁻¹²) or femtofarads (10⁻¹⁵)? (Real TSVs are tens of fF; commit to a guess before reading on.)

Step 1. $ε = ε_{r} ε_{0} = 3.9 \times 8.85 \times 1 0^{- 12} = 3.4515 \times 1 0^{- 11}$ F/m. Why this step? The formula needs the absolute permittivity of the liner, not the relative number. Step 2. $ln (b / a) = ln (3/2.5) = ln (1.2) = 0.1823$ . Why this step? This log is the pure-geometry factor from the coax derivation — it measures how many "e-foldings" of radius separate core and silicon. Step 3. $C = \frac{2 π ε h}{ln ( b / a )} = \frac{2 π ( 3.4515 \times 1 0 ^{- 11} ) ( 50 \times 1 0 ^{- 6} )}{0.1823} = 5.95 \times 1 0^{- 14}$ F. Why this step? Direct substitution into the boxed formula.

Verify: $5.95 \times 1 0^{- 14}$ F $= 59.5$ fF — tens of femtofarads, matching the "real TSVs are tens of fF" sanity note. Units: (F/m)·(m) = F. ✓

Cell B — Degenerate: thin oxide $b \to a$

Worked example Ex 2 — what happens as the liner gets vanishingly thin?

Keep $a = 2.5 μ m$ , $h = 50 μ m$ , $ε_{r} = 3.9$ , but shrink the liner so $b = 2.55 μ m$ (only $50$ nm of oxide). Forecast: will $C$ go up or down versus Ex 1? Watch the denominator.

Step 1. $ln (b / a) = ln (2.55/2.5) = ln (1.02) = 0.019803$ . Why this step? As $b \to a$ the ratio $b / a \to 1$ and $ln (1) = 0$ ; the log collapses toward zero. Step 2. $C = \frac{2 π ( 3.4515 \times 1 0 ^{- 11} ) ( 50 \times 1 0 ^{- 6} )}{0.019803} = 5.476 \times 1 0^{- 13}$ F $= 547.6$ fF. Why this step? Same formula; the tiny denominator blows the capacitance up ~9× versus Ex 1.

Verify (limit reasoning): in the limit $b \to a$ , $ln (b / a) \to 0^{+}$ so $C = \frac{2 π ε h}{ln ( b / a )} \to + \infty$ . Physically: a paper-thin insulator between two conductors is a huge capacitor — exactly a parallel-plate capacitor whose plates almost touch. So the degenerate case is not "no capacitance" but infinite capacitance, the worst thing for signal speed. This is why liners can't be made arbitrarily thin. ✓

Cell C — Degenerate: zero length $h \to 0$

Worked example Ex 3 — the wafer-thinning limit

Same $a = 2.5 μ m$ , $b = 3 μ m$ , $ε_{r} = 3.9$ . Now ask: as we grind the wafer thinner, $h \to 0$ . What does $C$ do, and what is $C$ at a nearly-zero $h = 1 μ m$ ? Forecast: the parent note said thinning the wafer shrinks $C$ . So predict the trend, then the number.

Step 1. $C = \frac{2 π ( 3.4515 \times 1 0 ^{- 11} ) ( 1 \times 1 0 ^{- 6} )}{0.1823} = 1.19 \times 1 0^{- 15}$ F $= 1.19$ fF. Why this step? $C \propto h$ directly, so cutting $h$ from 50 µm to 1 µm cuts $C$ by 50×. From Ex 1's 59.5 fF that's ≈1.19 fF. ✓ Step 2. Take the limit: as $h \to 0$ , $C \to 0$ . Why this step? A via of zero length is no via at all — there is no cylindrical surface to store charge on. The formula is continuous and well-behaved at this edge: no blow-up, just a clean approach to zero.

Verify: $1.19$ fF is 1/50 of $59.5$ fF within rounding: $59.5/50 = 1.19$ . ✓ The limit $h \to 0 \Rightarrow C \to 0$ confirms the physics: thinner wafer = lower load = faster, which is why we thin.

Cell D — Energy per switch

Worked example Ex 4 — energy saved per bit (3D vs 2D)

Signalling at $V = 0.9$ V. Long cross-chip 2D wire $C_{2 D} = 1$ pF $= 1 \times 1 0^{- 12}$ F. Our TSV $C_{3 D} = 60$ fF $= 6 \times 1 0^{- 14}$ F. Forecast: guess the energy-saving ratio — 2×? 10×? 100×?

Step 1. $E_{2 D} = \frac{1}{2} C_{2 D} V^{2} = \frac{1}{2} (1 \times 1 0^{- 12}) (0.9)^{2} = 4.05 \times 1 0^{- 13}$ J. Why this step? Every time a wire flips, you charge its capacitance to $V$ ; the energy stored (and later dumped as heat) is $\frac{1}{2} C V^{2}$ . Step 2. $E_{3 D} = \frac{1}{2} (6 \times 1 0^{- 14}) (0.9)^{2} = 2.43 \times 1 0^{- 14}$ J. Why this step? Same law, tiny TSV capacitance. Step 3. ratio $= E_{2 D} / E_{3 D} = 4.05 \times 1 0^{- 13} /2.43 \times 1 0^{- 14} = 16.67$ . Why this step? The $V^{2}$ cancels, so the energy ratio is just the capacitance ratio $1000/60 \approx 16.7$ .

Verify: $C$ -ratio $1 pF /60 fF = 1000/60 = 16.67$ , equals the energy ratio — since $V$ is shared, energy tracks $C$ exactly. Units: F·V² = C·V = J. ✓ ~17× less energy per bit.

Cell E — Sign / direction of change (which knob helps?)

Worked example Ex 5 — sensitivity: I doubled the oxide thickness, what happened to

$C$ ? Start at Ex 1 ( $a = 2.5$ , $b = 3$ , so oxide is $0.5 μ m$ thick, $C_{1} = 59.5$ fF). Now double the oxide thickness: $b = 3.5 μ m$ (oxide $= 1.0 μ m$ ). Find the new $C$ and its sign of change. Forecast: thicker insulator — does $C$ rise or fall? By roughly how much?

Step 1. $ln (b / a) = ln (3.5/2.5) = ln (1.4) = 0.3365$ . Why this step? Bigger $b$ ⇒ bigger ratio ⇒ bigger log ⇒ bigger denominator. Step 2. $C_{2} = \frac{2 π ( 3.4515 \times 1 0 ^{- 11} ) ( 50 \times 1 0 ^{- 6} )}{0.3365} = 3.222 \times 1 0^{- 14}$ F $= 32.2$ fF. Why this step? Same formula; the larger denominator shrinks $C$ . Step 3. Change: $C_{2} / C_{1} = 32.2/59.5 = 0.541$ — capacitance dropped to 54%. Why this step? Confirms the parent note's "thicker oxide → smaller $C$ → faster." Note it did not halve exactly — because $C$ depends on $ln (b / a)$ , not on the oxide thickness linearly. Doubling the gap only raised the log from $0.182$ to $0.336$ (≈1.85×), so $C$ fell by $1/1.85 \approx 0.54$ .

Verify: $0.1823/0.3365 = 0.5418$ , matching the $C$ -ratio $0.541$ (the $2 π ε h$ prefactor cancels). ✓ Sign of effect: negative — thicker liner always lowers $C$ , but with diminishing (logarithmic) returns.

Cell F — I/O counting, edge vs area

Worked example Ex 6 — perimeter links vs whole-face links

A square die of side $L = 10$ mm, pad pitch $p = 40 μ m$ . Count edge-only I/O ( $N_{2 D} = 4 L / p$ ) and full-face TSV I/O ( $N_{3 D} = L^{2} / p^{2}$ ). Forecast: the parent said ~60×. Predict the two counts before computing.

Step 1. Convert: $L = 10000 μ m$ , $p = 40 μ m$ . Why this step? Both quantities must be in the same unit before dividing. Step 2. $N_{2 D} = 4 L / p = 4 (10000) /40 = 1000$ . Why this step? Connections leave only through the 1D perimeter ( $4 L$ of edge), spaced $p$ apart, so the count grows linearly in $L$ . Step 3. $N_{3 D} = (L / p)^{2} = (10 000/40)^{2} = 25 0^{2} = 62500$ . Why this step? TSVs tile the 2D face ( $L^{2}$ area) on a $p \times p$ grid, so the count grows quadratically in $L$ . Step 4. Ratio $= 62 500/1000 = 62.5$ . Why this step? Area beats perimeter by $L / (4 p) = 10 000/160 = 62.5$ .

Verify: $N_{3 D} / N_{2 D} = (L^{2} / p^{2}) / (4 L / p) = L / (4 p) = 10 000/ (4 \cdot 40) = 62.5$ . ✓ ~60× more parallel links — this is the seed of HBM's ultra-wide bus.

Cell G — Real-world word problem

Worked example Ex 7 — HBM stack bandwidth, end to end

One HBM stack presents a 1024-bit-wide vertical bus (via TSVs), each pin running at 3.2 Gbps (gigabits per second). A GPU uses 4 such stacks. What total bandwidth (in TB/s) does it deliver? Forecast: single stack ~0.4 TB/s. Four stacks — guess before computing.

Step 1. Per-stack bit rate $= 1024 \times 3.2 \times 1 0^{9} = 3.2768 \times 1 0^{12}$ bit/s. Why this step? Bandwidth = bus width (parallel lanes) × per-lane rate. The width of 1024 is only feasible because TSVs give area-scaled I/O. Step 2. Convert bits→bytes (÷8): $3.2768 \times 1 0^{12} /8 = 4.096 \times 1 0^{11}$ B/s $= 409.6$ GB/s. Why this step? Data sheets quote bytes; 8 bits = 1 byte. Step 3. Four stacks: $4 \times 409.6 = 1638.4$ GB/s $= 1.6384$ TB/s. Why this step? Stacks operate in parallel, so bandwidths add.

Verify: $1024 \times 3.2 \times 1 0^{9} \times 4/8 = 1.6384 \times 1 0^{12}$ B/s $= 1.64$ TB/s. Units: bit/s ÷ (bit/byte) = byte/s. ✓ Over a terabyte per second — the payoff of vertical, area-scaled connectivity.

Cell H — Thermal limiting case (the real ceiling)

Worked example Ex 8 — how hot does a buried logic layer get?

Fourier's law of heat conduction: $Q = \frac{k A Δ T}{t} \Rightarrow Δ T = \frac{Qt}{k A}$ , where $Q$ is heat power (W) crossing a slab, $k$ its thermal conductivity (W/m·K), $A$ the area, $t$ the thickness the heat must cross. Silicon $k = 150$ W/m·K. A buried die dissipates $Q = 20$ W over area $A = 1 cm^{2} = 1 \times 1 0^{- 4} m^{2}$ , and heat must climb through $t = 100 μ m$ of stacked silicon to escape. Forecast: a few °C? tens of °C? Predict before solving.

Step 1. $Δ T = \frac{Qt}{k A} = \frac{( 20 ) ( 100 \times 1 0 ^{- 6} )}{( 150 ) ( 1 \times 1 0 ^{- 4} )}$ . Why this step? Solve Fourier's law for temperature rise: more power or thicker stack → hotter; better conductor or bigger area → cooler. Step 2. Numerator $= 20 \times 1 0^{- 4} = 2 \times 1 0^{- 3}$ ; denominator $= 150 \times 1 0^{- 4} = 1.5 \times 1 0^{- 2}$ . Why this step? Keep numerator and denominator separate to avoid slips. Step 3. $Δ T = 2 \times 1 0^{- 3} /1.5 \times 1 0^{- 2} = 0.133$ K per single buried layer. Why this step? Small per layer — but $Δ T \propto Q t$ : double the layers ⇒ roughly double both $Q$ and $t$ ⇒ ~4× the rise, and hotspots (small $A$ ) make it far worse. This is the wall that caps logic-on-logic stacking.

Verify: $Δ T = 2 \times 1 0^{- 3} /1.5 \times 1 0^{- 2} = 0.1333$ K. Units: (W·m)/((W/m·K)·m²) = K. ✓ See Thermal Management in ICs for why this scaling forces memory-on-logic pairing.

Cell I — Exam twist (back-solve)

Worked example Ex 9 — "Design the liner": solve for

$b$ to hit a target An exam gives you a TSV budget: you must keep $C \leq 40$ fF. Given $a = 2.5 μ m$ , $h = 50 μ m$ , $ε_{r} = 3.9$ , find the minimum oxide outer radius $b$ (hence the minimum liner thickness). Forecast: from Ex 1 (60 fF at $b = 3$ ) and Ex 5 (32 fF at $b = 3.5$ ), the answer must lie between $b = 3$ and $b = 3.5 μ m$ .

Step 1. Rearrange the formula for the log: $ln (b / a) = \frac{2 π ε h}{C}$ . Why this step? $b$ is trapped inside a logarithm, so first isolate $ln (b / a)$ , then undo the log. Step 2. $ln (b / a) = \frac{2 π ( 3.4515 \times 1 0 ^{- 11} ) ( 50 \times 1 0 ^{- 6} )}{40 \times 1 0 ^{- 15}} = \frac{1.0844 \times 1 0 ^{- 14}}{4 \times 1 0 ^{- 14}} = 0.2711$ . Why this step? Plug the target $C = 40$ fF into the isolated form. The numerator $2 π ε h$ is the same prefactor from Ex 1. Step 3. Undo the log with $exp$ : $b / a = e^{0.2711} = 1.3114 \Rightarrow b = 2.5 \times 1.3114 = 3.278 μ m$ . Why this step? $ln$ and $e^{x}$ are inverses — $e^{0.2711}$ answers "what ratio has this log?" Step 4. Minimum liner thickness $= b - a = 3.278 - 2.5 = 0.778 μ m$ . Why this step? The oxide is the ring between core and outer radius.

Verify: plug $b = 3.278$ back: $ln (3.278/2.5) = ln (1.3112) = 0.2710$ , giving $C = 1.0844 \times 1 0^{- 14} /0.2710 = 4.00 \times 1 0^{- 14}$ F $= 40$ fF. ✓ And $3.278$ lands between $3$ and $3.5$ as forecast. ✓ Since $C$ decreases with $b$ , any $b \geq 3.278 μ m$ satisfies $C \leq 40$ fF — so this is indeed the minimum.

Recall Quick self-test (reveal after answering)

As oxide gets vanishingly thin ( $b \to a$ ), does TSV capacitance go to zero or infinity? ::: To infinity — $ln (b / a) \to 0$ in the denominator (Ex 2). As the wafer is ground to zero thickness ( $h \to 0$ ), what happens to $C$ ? ::: It goes to zero, cleanly and continuously (Ex 3). Why does full-face TSV I/O beat edge I/O by the factor $L / (4 p)$ ? ::: Face count grows as area $L^{2}$ while edge count grows as perimeter $4 L$ ; their ratio is $L / (4 p)$ (Ex 6). To lower $C$ you thicken the oxide — why do returns diminish? ::: $C$ depends on $ln (b / a)$ , so doubling the gap raises the log less than 2× (Ex 5).

Connections

Parent: 3D stacking and through-silicon vias (TSV) (index 6.5.3)
Bandwidth payoff: High Bandwidth Memory (HBM)
Wire-delay motivation: Interconnect RC Delay, Moore's Law
The thermal wall: Thermal Management in ICs
Alternatives & context: Interposers and 2.5D Integration, Chiplets and Heterogeneous Integration, Chip Packaging