3D stacking and through-silicon vias (TSV): Foundations

This page assumes you know nothing. Every letter, ratio, and squiggle used in the parent topic is built here from the ground up, in the order that lets each one lean on the one before it.

0. The picture the whole topic lives in

Before any symbol, hold this image: a chip is a flat square of silicon covered in tiny switches (transistors) and thin metal wires connecting them. 3D stacking puts a second such square directly on top, and drills tunnels straight down to connect them.

Figure — 3D stacking and through-silicon vias (TSV)

Everything below is the vocabulary needed to describe how the elevator between floors works and why the elevator wins.

1. Length and how we measure the tiny — µm

Powers of ten you will meet, smallest (most negative exponent) first:

Symbol	Name	Meaning	Where it shows up
$f$	femto	$1 0^{- 15}$	capacitance (fF)
$p$	pico	$1 0^{- 12}$	capacitance (pF), delays
$n$	nano	$1 0^{- 9}$	ordinary metal vias, transistor sizes
$μ$	micro	$1 0^{- 6}$	TSV width & height
$m$	milli	$1 0^{- 3}$	full chip width $L$

These prefixes are just stickers on the front of a number telling you which power of ten to multiply by. Nothing more mysterious.

2. Multiplying, dividing, and the log — the shapes of growth

The parent note repeatedly says one thing "grows like" another. That phrase means: if I make one quantity bigger, how does the other respond? Three response-shapes appear.

Recall Why do we care that

$ln$ grows slowly here? Because it sits in the denominator of the capacitance formula. A slowly-changing denominator means capacitance is forgiving of small manufacturing variation in the oxide thickness. ::: Slow-growing denominator → stable, predictable capacitance.

3. Charge, voltage, current — the electrical alphabet

Every symbol in the physics derivations comes from four everyday electrical ideas. Picture water in pipes.

4. Capacitance $C$ — the star of the whole topic

The figure below is this definition drawn as two water tanks — the narrow tank (small $C$ , fills with little charge) versus the wide tank (big $C$ , guzzles charge for the same rise). Read it left-to-right before continuing; every later "big tank / tiny tank" phrase points back to this picture.

Formula Building the TSV capacitance formula from geometry + permittivity

WHY: the parent note keeps quoting $C_{TSV}$ , and D1 promised to build it. Here it is, from the three nested cylinders (core radius $a$ , oxide out to $b$ , height $h$ ) and the material knob $ε$ from §6. A charge $λ$ per unit length on the core makes an electric field that (by Gauss's law) falls off as $E_{field} (r) = \frac{λ}{2 π ε r}$ at distance $r$ . Adding up (integrating) the field-slope from the core out to the oxide edge gives the voltage across the oxide: $V = \int_{a}^{b} E_{field} d r = \frac{λ}{2 π ε} ln \frac{b}{a} .$ Since $C = Q / V$ and total charge $Q = λh$ , the $λ$ cancels and leaves $C_{TSV} = \frac{2 π ε h}{ln ( b / a )}$ Read it: thicker oxide (bigger $b / a$ ) → bigger $ln$ in the denominator → smaller $C$ → faster, lower-energy tunnel. Taller via (bigger $h$ ) → bigger $C$ — which is exactly why the wafer is thinned to shrink $h$ .

5. Resistance $R$ and the RC product — where delay is born

Recall If a wire's length triples, how does its RC delay change?

$\times 9$ . ::: Because delay $\propto ℓ^{2}$ and $3^{2} = 9$ .

6. Geometry symbols of the tunnel — $a$ , $b$ , $h$ , $L$ , $p$

The TSV is modelled as three nested cylinders. Naming their radii lets the formulas be exact.

7. Perimeter vs area — why $L$ vs $L^{2}$ is the bandwidth story

8. Heat: $Q_{heat}$ , $k$ , $A$ , $t$ , $Δ T$ — the villain that stops infinite stacking

Prerequisite map

Each foundation box feeds the topic exactly where the parent note uses it: growth-shapes + $R$ + $C$ make the delay argument, geometry + permittivity make the capacitance formula, perimeter-vs-area makes the bandwidth argument, and heat is the counterweight that limits it all.

The delay story continues in Interconnect RC Delay; the "why did wires stop shrinking" backstory is Moore's Law; the side-by-side cousin of stacking is Interposers and 2.5D Integration; mixing dies from different processes is Chiplets and Heterogeneous Integration; the heat wall is detailed in Thermal Management in ICs; and how it all gets sealed into a product is Chip Packaging.

Equipment checklist

Self-test: can you say each aloud before revealing?

How to read the "::=" sign

"is defined as" — the left side is the new word, the right side its plain-words meaning.

1 μ m

in metres

1 0^{- 6} m

(one millionth of a metre).

The two meanings of the letter "m"

prefix milli (

1 0^{- 3}

) when in front of a unit; the unit metre when standing alone.

What

y \propto x^{2}

means for doubling

x

y

becomes 4× larger.

Why

ln

appears in the TSV formula and why we don't sweat its exact value

it grows very slowly, so capacitance is forgiving of oxide-ratio variation.

Capacitance in one sentence

charge needed per volt of rise,

C = Q / V

; the "tank's cross-section."

The difference between

E_{field}

and

E

E_{field}

is the electric field (a slope with direction); bare

E

is energy (a number of joules).

Energy to switch a capacitor

E = \frac{1}{2} C V^{2}

; the

\frac{1}{2}

is the average back-pressure discount.

The TSV capacitance formula

C_{TSV} = \frac{2 π ε h}{ln ( b / a )}

— from nested cylinders of radii

a

b

and height

h

Why wire delay grows like length squared

both

R \propto ℓ

and

C \propto ℓ

, and

τ = R C \propto ℓ^{2}

What

a

b

h

are on a TSV

copper-core radius, oxide-edge radius, tunnel height.

Why radii enter as the ratio

b / a

coaxial physics depends only on the proportion, not absolute size.

Permittivity

ε

in words

how easily an insulator passes an electric field; the material knob for

C

Perimeter vs area scaling

edge

\propto L

(few links), face

\propto L^{2}

(many links) → bandwidth win.

Fourier temperature rise

Δ T = Q_{heat} t / (k A)

; thicker/hotter stacks get hotter → the stacking limit.