3D stacking and through-silicon vias (TSV): Visual walkthrough

Step 0 — What is the object we are measuring?

WHAT we just did: named the parts. WHY: the formula only makes sense once you can point at $a$ , $b$ , $h$ on a drawing. WHAT IT LOOKS LIKE: figure s01 — copper (amber) core, cyan oxide ring, blueprint silicon around it.

Step 1 — Put charge on the wire, ask what field it makes

WHY this tool (the field): voltage is not something we can write down directly here — the gap is curved, not flat plates. But voltage is just field added up along a path. So to get $V$ , we must first get $E$ . The field is the stepping stone.

WHAT IT LOOKS LIKE: figure s02 — cyan field arrows shooting straight out from the copper line, longer (stronger) near the core, shorter far away.

Step 2 — Gauss's law gives the field's exact shape

Wrap an imaginary cylinder of radius $r$ and length $h$ around the copper (figure s03). The field is the same strength everywhere on its curved side (symmetry), and that side has area $2 π r h$ (circumference $2 π r$ times height $h$ ). Trapped charge is $λh$ . So:

$field at radius r E (r) \times area field pokes through 2 π r h = trapped charge / ε \frac{λh}{ε}$

Cancel $h$ , solve for $E$ :

$E (r) = \frac{λ}{2 π ε r}$

$λ$ — charge per length: more charge, stronger field.
$r$ — distance from centre: field fades like $1/ r$ as you move out. This is the key shape.
$2 π$ — comes from the circle's circumference; it's geometry, not physics.
$ε$ — how much the oxide "soaks up" field (Step 3).

WHAT we did: used symmetry to nail $E (r)$ exactly. WHY: now we have the stepping stone to voltage. WHAT IT LOOKS LIKE: figure s03 — dashed Gaussian cylinder, arrows equal all around its side.

Step 3 — What is $ε$ , and why the oxide's version matters

WHY it enters here: the field in Step 2 lives inside the oxide liner (between $a$ and $b$ ), so the $ε$ we use is the oxide's permittivity. This is the only place material choice sneaks into the formula — and it's why engineers hunt for low- $ε$ liners: they lower $C$ .

WHAT IT LOOKS LIKE: figure s04 — same field arrows shrinking when the gap is filled with oxide vs vacuum, showing $ε$ "softening" the field.

Step 4 — Add the field along a path to get voltage

$V = \int_{a}^{b} E (r) d r = \int_{a}^{b} \frac{λ}{2 π ε r} d r$

$\int_{a}^{b} \dots d r$ — "add the field over every sliver from $a$ to $b$ ."
The only thing changing inside is $\frac{1}{r}$ .

The integral of $\frac{1}{r}$ is the natural logarithm $ln$ . (Why $ln$ ? Because $ln$ is defined as the running area under $1/ r$ — it is the exact answer to "sum up $1/ r$ ." No other function does this.) So:

$V = \frac{λ}{2 π ε} [ln r]_{a}^{b} = \frac{λ}{2 π ε} ln \frac{b}{a}$

$ln \frac{b}{a}$ — the geometry factor: it only cares about the ratio of the two radii, not their absolute size. A thicker liner (bigger $b$ ) → bigger $ln (b / a)$ → bigger voltage for the same charge.

WHAT we did: turned field into voltage by integrating across the liner. WHY: $C = Q / V$ needs a $V$ , and now we have it. WHAT IT LOOKS LIKE: figure s05 — the $1/ r$ curve with the shaded area from $a$ to $b$ labelled "this area = voltage = $ln (b / a)$ ."

Step 5 — Divide: charge over voltage gives capacitance

Now assemble $C = Q / V$ . Recall $Q = λh$ (charge per length times height):

$C = \frac{Q}{V} = \frac{λh}{\frac{λ}{2 π ε} l n \frac{b}{a}}$

The $λ$ cancels top and bottom (capacitance never depends on how much charge you put on — that's the whole point of it being a fixed property of the geometry). Flipping the divided fraction:

$C_{TSV} = \frac{2 π ε h}{ln ( b / a )}$

WHAT IT LOOKS LIKE: figure s06 — the finished cross-section with each symbol pinned to the part it controls, plus arrows "↑h ⇒ ↑C" and "↑liner ⇒ ↓C."

Step 6 — Edge and degenerate cases (never leave a gap)

Intuition Push the formula to its limits

A formula you trust must survive the extremes. Look at figure s07.

Very thin liner, $b \to a$ : then $b / a \to 1$ and $ln (1) = 0$ , so $C \to \infty$ . Correct — a vanishingly thin insulator is a near short; the two conductors almost touch and store enormous charge. Physically this is the failure mode where a TSV leaks into the substrate.
Very thick liner, $b ≫ a$ : $ln (b / a)$ grows large, $C \to 0$ . Also correct — pull the wall far away and there's almost no coupling. But a fat liner steals precious area, so real designs pick a modest ratio (e.g. $a = 2.5 μ m$ , $b = 3 μ m$ ).
Zero height, $h \to 0$ (an infinitely thin die): $C \to 0$ . A via with no length has no wall area to couple through. This is the ideal we chase by thinning — smaller $h$ , smaller $C$ .
$a = 0$ (no copper): $ln (b /0) = ln (\infty) = \infty$ , so $C \to 0$ — with no conductor there is nothing to charge. Sanity holds.

The one-picture summary

Figure s08 stitches the whole chain into one flow: charge on copper → Gauss gives $E = λ /2 π ε r$ → integrate across the liner gives $V = \frac{λ}{2 π ε} ln \frac{b}{a}$ → divide $Q / V$ gives $C = \frac{2 π ε h}{l n ( b / a )}$ , with the design levers ( $h$ , liner thickness, $ε$ ) hanging off the result.

Recall Feynman retelling — say it back in plain words

A TSV is a copper straw pushed through a chip, wrapped in a thin insulating sleeve, with the chip's silicon body as a wall on the outside. Copper and silicon are two conductors with insulator between — that's a capacitor, and a capacitor slows signals and burns energy, so we want its number small. To find that number I asked "how much charge per volt?" I put charge on the copper, and because the shape is a perfect cylinder I used Gauss's law to instantly get the field: it points outward and weakens as $1/ r$ . To turn that field into a voltage I added it up across the insulating sleeve — adding $1/ r$ gives a logarithm, so the voltage carries an $ln (b / a)$ , where $a$ is the copper's radius and $b$ is the outside of the sleeve. Dividing charge by voltage, the charge amount cancels (capacitance is pure geometry), leaving $C = \frac{2 π ε h}{l n ( b / a )}$ . Reading it: a taller via ( $h$ ) means more $C$ (bad) — so we grind the wafer thin. A thicker sleeve or lower-permittivity material means less $C$ (good). And the extremes behave: touching conductors give infinite $C$ , a far wall or zero height gives zero $C$ . That's the entire result, honestly earned.

Recall Quick self-test

Why does thinning the wafer lower TSV capacitance? ::: $C \propto h$ ; less height $h$ means less wall area coupling copper to silicon, so directly less $C$ . Why is there a logarithm in the formula? ::: Voltage is the field integrated across the liner, and the field goes as $1/ r$ ; the integral of $1/ r$ is $ln$ , evaluated from $a$ to $b$ giving $ln (b / a)$ . What does $ε$ physically represent and why prefer it low? ::: The liner's permittivity — how readily it stores field; low- $ε$ liners store less charge, giving lower $C$ , faster and lower-energy signals.

See also: Interconnect RC Delay (why $C$ costs time and energy), High Bandwidth Memory (HBM) and Interposers and 2.5D Integration (where thousands of these vias run in parallel), Thermal Management in ICs (the wall this all runs into), and Chiplets and Heterogeneous Integration.