3D stacking and through-silicon vias (TSV): Question bank

Recall What a TSV actually is (one-line refresher before you start)

A Through-Silicon Via is a copper-filled tunnel drilled through the transistor-bearing silicon body of a die, oxide-lined so it doesn't short to the substrate, connecting that die to the one stacked above or below.

Definition Every symbol used on this page — defined once, up front

The trap questions below lean on three formulas. Before you touch them, pin down what each letter is and its units. Look at the cross-section figure while reading this list.

$a$ ::= inner radius of the copper core of the TSV (metres). The metal that actually carries the signal.
$b$ ::= outer radius of the oxide liner (metres), i.e. distance from the via centre out to where the grounded silicon begins. So $b - a$ is the liner thickness.
$ε$ ::= absolute permittivity of the oxide liner (farads per metre, F/m), $ε = ε_{r} ε_{0}$ . It measures how much charge the insulator stores per volt.
$h$ ::= height (length) of the via through the silicon (metres) — set by wafer thickness.
$ℓ$ ::= length of a signal wire (metres). For a horizontal route $ℓ \sim$ mm; for a vertical TSV $ℓ = h \sim 50 μ m$ .
$Q$ ::= heat power dumped into the stack (watts, W).
$t$ ::= stack thickness the heat must conduct through (metres).
$k$ ::= thermal conductivity of the material (watts per metre-kelvin, W/(m·K)).
$A$ ::= cross-sectional area the heat flows through (square metres, m²).
$Δ T$ ::= temperature rise of the buried hotspot (kelvin, K).

Figure — 3D stacking and through-silicon vias (TSV)

Formula The three laws these traps test (with the

why of each dependence) 1 · TSV capacitance (coax model). The copper core, oxide, and grounded silicon are three concentric cylinders — exactly a coaxial capacitor. Sketch it in the figure: field lines leave the core radially, cross the oxide, and land on the silicon. $C_{TSV} = \frac{2 π ε h}{l n ( b / a )}$ Why $ln (b / a)$ ? The radial field from a line charge is $E (r) = \frac{λ}{2 π ε r}$ — it weakens as $1/ r$ moving outward. Adding up (integrating) that field from $a$ to $b$ to get the voltage gives $\int_{a}^{b} \frac{d r}{r} = ln (b / a)$ . The logarithm is simply the fingerprint of a $1/ r$ field over a cylinder; a bigger $b / a$ (thicker oxide) means more voltage per charge, hence less capacitance. Full derivation lives in the parent note 3D stacking and through-silicon vias (TSV). 2 · Wire delay law. $τ \propto R C \propto ℓ^{2}$ . Why $R \propto ℓ$ and $C \propto ℓ$ ? A wire of fixed cross-section has resistance proportional to its length (longer resistor = more ohms) and capacitance proportional to its length (uniform capacitance-per-unit-length along the wire). Multiply the two length-proportional terms and the delay grows like $ℓ^{2}$ . 3 · Fourier heat law. $Δ T = \frac{Q t}{k A}$ . A hotspot's temperature rise grows with the power $Q$ and the thickness $t$ it must push heat through, and falls with better conductivity $k$ and wider flow area $A$ . This lumped form assumes heat flows straight down through a fixed area $A$ — a good picture for a broad, uniform layer.

True or false — justify

Every "true/false" answer below states the verdict and the reason — a bare T/F earns nothing.

A TSV's capacitance to the substrate goes down if you make the oxide liner thicker.

True — thicker oxide means a larger outer radius

b

, and

C = \frac{2 π ε h}{l n ( b / a )}

shrinks as

ln (b / a)

grows; a smaller cap means faster, lower-energy signalling.

Thinning the wafer helps mainly because it makes the chip lighter.

False — thinning shrinks the via height

h

, and since

C \propto h

, a shorter via has less capacitance (and the tip is exposed for bonding). Weight is irrelevant.

Wire delay across a 2D chip scales linearly with wire length.

False — because both resistance

R \propto ℓ

and capacitance

C \propto ℓ

, the delay

τ \propto R C \propto ℓ^{2}

; it grows with the square of length, which is the whole reason short vertical hops win.

A 3D stack gives more I/O than a 2D chip because it uses the whole face instead of just the edge.

True — 2D I/O leaves through a perimeter (

N_{2 D} \propto L

), while TSVs cover an area (

N_{3 D} \propto L^{2}

); for a 10 mm die at 40 µm pitch that's ~1000 vs ~62,500 links.

2.5D integration puts TSVs through the compute dies themselves.

False — in 2.5D the TSVs live in the interposer underneath; the compute dies sit side by side on it and are not drilled through. Only true 3D drills through the compute dies.

Adding more stacked layers always increases achievable performance.

False — shorter wires help, but total power lands in the same footprint, so

Δ T = Qt / (k A)

rises and clocks must throttle, which can erase the speedup. Heat, not wiring, sets the ceiling.

The oxide liner and the diffusion barrier serve the same purpose.

False — the oxide electrically insulates copper from the semiconducting silicon (prevents shorting); the barrier (e.g. TaN) chemically blocks copper atoms from diffusing into silicon and poisoning transistors. Two different failures.

A TSV is essentially the same object as a normal metal via between wiring layers.

False — an ordinary via connects metal layers inside the interconnect stack at nanometre scale; a TSV passes through the silicon substrate at micron scale (~1000× bigger), needing an oxide liner, wafer thinning, and a keep-out zone.

Memory-on-logic 3D stacking is thermally easier than logic-on-logic.

True — memory dies dissipate far less power per area than logic, so stacking them adds little heat to the shared footprint; two hot logic dies would compound

Q

and drive

Δ T

up fast.

HBM reaches TB/s bandwidth mainly by clocking each wire extremely fast.

False — it uses a very wide bus (e.g. 1024 bits) at only modest per-pin rates; the width is affordable precisely because TSVs give area-scaled I/O, not because any single lane is heroic.

Spot the error

Each prompt contains a planted mistake; the answer names it and corrects it.

"We drill the via, fill it with copper, and we're done — no need to line the wall."

Error: skips the oxide liner. Silicon conducts enough to short the copper to the substrate; without the insulating liner (plus a barrier) the TSV fails electrically and copper poisons nearby transistors.

"To lower TSV capacitance we should use an oxide with a higher permittivity."

Error:

C \propto ε

, so a higher permittivity liner gives more capacitance. You want a low-

ε

(low-k) liner to reduce the load.

"Longer TSVs are better because more length means more metal and lower resistance."

Error: length raises capacitance (

C \propto h

) and the coax cap is the dominant penalty here; that's why we thin the wafer to shorten

h

, not lengthen it.

"Because vertical hops are ~50 µm and horizontal routes are ~5 mm, the delay improves by about 100×."

Error: delay scales as length squared, so the ratio is

(50/5000)^{2} = 1 0^{- 4}

— about a 10,000× improvement, not 100×.

"2.5D and 3D both stack dies on top of each other, they just have different names."

Error: 2.5D places dies side by side on an interposer (TSVs in the interposer); only 3D stacks dies directly atop one another with TSVs through the dies themselves.

"The keep-out zone exists because the TSV needs room for its electrical field."

Error: the keep-out zone is a mechanical-stress exclusion — copper and silicon expand differently, and the resulting stress would shift transistor behaviour, so no active devices sit right next to the via.

"Bandwidth = bus width, so a 1024-bit HBM bus gives 1024 bytes per second."

Error: bandwidth = width × per-pin rate, and bits must be divided by 8 for bytes. At 3.2 Gbps/pin that's ~410 GB/s per stack, not 1024 B/s.

Why questions

Why does data want to travel vertically through a TSV rather than horizontally across the die?

Because wire delay

\propto ℓ^{2}

(with

ℓ

the wire length): a 50 µm vertical hop replaces a millimetres-long horizontal route, cutting delay and switching energy by orders of magnitude for the same signal.

Why can 3D stacking mix an old cheap process with a new expensive one?

Each die is fabricated separately and only joined afterward, so you can put memory/analog on a mature low-cost node and logic on a leading node — "right tool per layer" (heterogeneous integration).

Why does the TSV behave like a coaxial capacitor rather than an ideal wire?

The copper core (

a

), oxide liner (out to

b

), and grounded silicon form concentric conductors/dielectric — exactly a coax geometry — so charge on the core induces a cap to the substrate that loads and slows the signal.

Why does the capacitance depend on

ln (b / a)

and not simply on

(b - a)

The radial field of a line charge falls off as

1/ r

, so summing it across the oxide integrates

1/ r

, which gives a logarithm; the log of the ratio

b / a

is the natural fingerprint of cylindrical geometry, not the plain gap width.

Why do 2D chips run out of I/O as they get bigger while 3D chips scale better?

2D links leave through the edge, which grows only like the perimeter

L

, while TSV links cover the whole face, growing like the area

L^{2}

— so face I/O outpaces edge I/O as

L

increases.

Why is heat the true limiting wall for aggressive 3D stacking?

Stacking piles more power

Q

into the same footprint, and from

Δ T = Qt / (k A)

the temperature rise grows with the conducting thickness

t

, forcing clock throttling that cancels the wiring gains.

Why does a TSV need wafer thinning that an ordinary metal via never requires?

A TSV must reach all the way through the silicon body and expose its tip for bonding ("via reveal"); an ordinary via lives inside the thin interconnect stack and never traverses the substrate.

Edge cases

What happens to the TSV capacitance formula if the oxide becomes vanishingly thin (

b \to a

ln (b / a) \to 0

, so

C \to \infty

— a physically-degenerate case meaning the copper is essentially touching the silicon, i.e. no insulation and effectively a short. It signals liner failure.

If you thin the wafer toward zero height (

h \to 0

), what does the model predict, and is it realistic?

C = \frac{2 π ε h}{l n ( b / a )} \to 0

, so capacitance vanishes; but there's a floor — you can't thin below mechanical/structural limits, and other parasitics and the bond joint dominate, so real caps plateau in the tens of fF.

For a 3D stack whose active layers dissipate almost no power (e.g. all low-power memory), what limits performance instead of heat?

Thermal

Δ T

becomes tiny, so the limit shifts to I/O and interconnect: TSV pitch, bond yield, and available bandwidth — the good regime that makes memory-on-logic (HBM) practical.

What if a die's power all comes from a single tiny hotspot rather than being spread out?

The lumped

Δ T = Qt / (k A)

assumes heat flows straight down through a fixed area

A

; a point source instead spreads sideways, so the true model needs a spreading resistance and the effective

A

grows with depth — the simple formula over-predicts

Δ T

if you naïvely plug in the hotspot area, and under-predicts if you use the whole die. Use it only where the heat source roughly fills

A

As pad/TSV pitch

p

shrinks toward zero, what caps the

N_{3 D} = L^{2} / p^{2}

I/O count in practice?

Manufacturing and stress limits: sub-micron pitch runs into bonding alignment, keep-out-zone overlap, and yield loss, so the

1/ p^{2}

growth saturates long before

p \to 0

What does the

N_{3 D} \propto L^{2}

N_{2 D} \propto L

comparison predict for a very small die where

L

is only a few pad-pitches wide?

The advantage nearly vanishes — for small

L

the face holds few TSVs and edge I/O is comparable, so 3D's area benefit only pays off once the die is large enough for many face connections.

Recall Fastest self-check before an exam

Delay law? ::: $τ \propto R C \propto ℓ^{2}$ ( $ℓ$ = wire length) — squared, so short hops win big. I/O scaling 2D vs 3D? ::: perimeter $L$ vs area $L^{2}$ . Real 3D ceiling? ::: heat, via $Δ T = Qt / (k A)$ . 2.5D vs 3D in one word? ::: beside (interposer) vs atop (through-die).

See also: High Bandwidth Memory (HBM) · Interposers and 2.5D Integration · Interconnect RC Delay · Chiplets and Heterogeneous Integration · Thermal Management in ICs · Chip Packaging