We care about two things: energy per bit and achievable bandwidth.
Step 1 — Model a wire as a capacitor.
Why? Moving a signal means charging/discharging the wire's capacitance C. A wire of length L has:
C=c⋅L
where c is capacitance per unit length (F/m). Why this step? Capacitance grows with how much conductor there is, i.e. with length.
Step 2 — Energy to send one bit.
Charging a capacitor C to voltage V costs energy:
Ebit=21CV2=21cLV2Why? Standard capacitor charging energy 21CV2. So energy scales linearly with lengthL.
Step 3 — Compare interposer vs PCB.
Silicon interposer wires are ~100× shorter (µm not mm) and the fine geometry lowers c. So:
EPCBEinterposer∼LPCBLint≪1
Roughly an order of magnitude less energy per bit.
Step 4 — Bandwidth from parallelism.
Total bandwidth is:
BW=Nwires×fsignal
Because interposer wires can be packed at ~1 µm pitch vs ~100 µm on PCB, Nwires jumps ~1002 if you count 2D area, or ~100× per edge length. This is why HBM (High Bandwidth Memory) needs an interposer — it uses a 1024-bit-wide bus that no PCB could route.
It's a passive silicon substrate under the chiplets that carries ultra-dense, short wiring (and TSVs) to connect chiplets at high bandwidth and low energy.
Difference between 2.5D and 3D packaging?
2.5D = chiplets side-by-side on an interposer (horizontal). 3D = active dies stacked vertically on top of each other.
Why do smaller chiplets improve yield?
Yield Y=e−DA falls with die area A; splitting a big die into small ones means each has higher yield and defects waste less silicon.
Formula for energy per bit on a wire, and what it implies?
Ebit=21cLV2; energy scales with wire length, so short interposer wires save energy.
What is a TSV and which direction does it go?
Through-Silicon Via — a vertical copper via passing through the silicon thickness to connect layers/package below.
Why does HBM require an interposer?
Its ~1024-bit-wide bus needs thousands of fine-pitch wires that a PCB (~100 µm pitch) cannot route; only chip-grade interposer wiring (~1 µm) can.
What is the reticle limit and why does it matter?
The max area (~858 mm²) a lithography exposure can pattern; you can't make a monolithic die bigger, forcing chiplet approaches.
Is a classic interposer active or passive?
Passive — just wiring and TSVs, no transistors (active interposers with logic are a newer exception).
Recall Feynman: explain it to a 12-year-old
Imagine building a huge LEGO castle out of one giant piece — if any tiny part is broken, the whole thing is ruined and you throw it all away. Instead, build it from small bricks: if one brick is bad, you toss just that brick. Now you need the bricks to talk to each other really fast, so you put them all on a special baseplate covered with thousands of tiny wires — much better than long floppy cables between far-apart pieces. That baseplate is the interposer, the small bricks are chiplets, and putting them side-by-side on it is 2.5D packaging.
Dekho, jab ek single chip bahut bada ho jaata hai to do problem aati hain: pehla, bade die par
defect padne ka chance zyada hota hai (yield gir jaati hai, chip mehnga), aur doosra, lithography
machine ek limit se bada pattern print hi nahi kar sakti (reticle limit). Solution simple hai — bade
chip ko chhote-chhote tukdon (chiplets) me kaat do. Har chiplet ko uske best process node par banao —
logic ko latest node par, IO/memory ko saste purane node par.
Ab problem yeh ki ye alag-alag chiplets aapas me tez baat kaise karein? Iske liye unke neeche ek
silicon interposer rakhte hain — ek passive silicon plate jisme chip-fab wali ultra-fine wiring
hoti hai (~1 micron pitch). PCB ki wire moti aur lambi hoti hai, isliye slow aur power-hungry. Interposer
ki wire chhoti aur bahut density me hoti hai, isliye hazaaron parallel lanes ban jaate hain — matlab
huge bandwidth, kam energy. Isi wajah se HBM memory (1024-bit wide bus) ko interposer chahiye hi chahiye;
PCB par itni wires route hi nahi hoti.
Naam "2.5D" isliye kyunki chiplets side-by-side (2D layout) rehte hain, lekin unke neeche ek extra
hidden wiring floor (.5) add ho jaata hai — TSV yaani Through-Silicon Via wo vertical copper via hai jo
interposer ke aar-paar neeche package tak jaata hai. Yaad rakho: 2.5D = chiplets bagal me, interposer
neeche. 3D matlab chips ek doosre ke upar stack — wo alag cheez hai. Energy formula E=21cLV2
bas yeh keh raha hai ki chhoti wire = kam energy, aur Y=e−DA keh raha hai chhota die = zyada yield.
Yehi do formula pura funda samjha dete hain.
