Co-packaged optics trends

WHAT is Co-packaged Optics?

The spectrum of integration:

Stage	Optics location	Electrical reach needed	Trend
Pluggable	Faceplate	~10–30 cm	Legacy
On-board optics (OBO)	Near ASIC on PCB	~5–10 cm	Interim
Co-packaged optics	On ASIC package	~1–5 mm	Emerging
Monolithic/optical I/O	On the die / chiplet	~0	Future

WHY do we need it? (Derive the pressure from first principles)

The whole motivation is energy and signal loss scaling faster than switch bandwidth.

Let's put numbers on it.

Worked example Faceplate power for a 51.2 Tb/s switch

Assume long-reach faceplate SerDes at $E_b \approx 5\ \text{pJ/bit}$ . $P = 5\times10^{-12}\ \tfrac{\text{J}}{\text{bit}} \times 51.2\times10^{12}\ \tfrac{\text{bit}}{\text{s}} = 256\ \text{W}$ Why this step? Multiply energy/bit by bits/s → joules/s = watts. That's ~256 W just for the electrical I/O, on top of the switch core. This is why the SerDes tax is unsustainable.

Now with CPO, the die-to-optics reach is millimeters, so $E_b$ can drop to ~ $1\ \text{pJ/bit}$ : $P = 1\times10^{-12}\times 51.2\times10^{12} = 51.2\ \text{W}$ Saving ≈ 200 W per switch — in this idealized $5\to1$ pJ/bit comparison that's an ~~80% cut in I/O link power**. In real deployments the whole-link saving is more modest (~~30–50%**), because CPO still keeps drivers, TIAs, DSP-lite and the optical devices themselves — the pJ/bit floor is not zero. Quote ~30–50% link-power reduction as the realistic headline; the 80% figure applies only to the SerDes-reach portion in this specific example.

HOW is CPO built?

Key enabling technologies (the 80/20 you must know):

Silicon photonics — build waveguides/modulators/detectors in CMOS-compatible processes → cheap, integrable, wafer-scale.
2.5D packaging — optical engine + ASIC on a shared interposer/organic substrate with fine-pitch bumps.
Advanced fiber attach — precise coupling (grating couplers / edge couplers) surviving thermal cycling.
Thermal management — optics hate heat; ring resonators drift, lasers redshift. Co-locating with a hot ASIC is the central engineering headache.

The trade-offs (steel-man the objections)

Trends timeline (the numbers to remember)

Bandwidth doubling ~every 2 years: 12.8 → 25.6 → 51.2 → 102.4 Tb/s switch ASICs.
Per-lane electrical SerDes: 112 Gb/s (PAM4) → 224 Gb/s — where copper reach really breaks.
Target CPO metric: < 5 pJ/bit end-to-end, aiming toward ~1 pJ/bit optical I/O.
Standards/consortia: OIF, CPO Collaboration, hyperscaler demos (e.g., 51.2 Tb/s CPO switches).

Recall Feynman: explain to a 12-year-old

Imagine your computer chip has to shout its messages to friends across a big room. The farther the shout, the more energy it takes and the more the words get garbled. Right now the "friends" (the parts that turn messages into light for fiber cables) sit way over at the door. Co-packaged optics brings those friends right next to the chip, so instead of shouting across the room, the chip just whispers a centimeter — same message, way less energy, and it comes out cleaner. The catch: those friends are now glued right next to the chip, so if one breaks you can't just swap it easily.

Flashcards

What is co-packaged optics?

Placing the optical transceiver on the same package/substrate as the switch/compute ASIC, shrinking the ASIC-to-optics electrical reach from ~cm to ~mm.

Primary motivation for CPO?

Electrical SerDes power and channel loss scale super-linearly with switch bandwidth; shortening electrical reach cuts energy/bit.

Formula for electrical interface power?

P = E_b \times B

(energy per bit × aggregate bandwidth).

51.2 Tb/s at 5 pJ/bit interface power?

5\text{pJ}\times51.2\text{Tb/s} = 256

Why does shorter electrical reach lower energy/bit?

Copper loss ∝ length (and ∝ ~√f + f); short reach needs far less equalization/DSP, so a tiny low-power SerDes suffices.

Why is the laser often kept external (ELS)?

Lasers are the least reliable, most temperature-sensitive component; keeping them serviceable/off the hot package improves reliability.

CPO vs monolithic optics?

CPO = separate chiplets on the same package; monolithic = optics built into the logic die itself.

Biggest downside of CPO vs pluggables?

Loss of field serviceability and modularity — a failed engine can mean scrapping the switch.

What are LPO/LRO and why do they exist?

Linear Pluggable/Receive Optics remove the DSP retimer but keep pluggable form factor — most of the power win with less serviceability risk.

Key enabling tech for CPO?

Silicon photonics + 2.5D/interposer packaging + precise fiber attach + thermal management.

Central engineering headache of CPO?

Thermal — optics (rings, lasers) drift with temperature but sit next to a very hot ASIC.

Realistic whole-link power saving from CPO?

Roughly 30–50% of link power (the ~80% figure applies only to the idealized SerDes-reach portion of a 5→1 pJ/bit example).

Connections

Silicon Photonics
SerDes and Wireline Links
2.5D and 3D Packaging
Pluggable Optical Modules (QSFP-DD, OSFP)
Linear Pluggable Optics (LPO)
Switch ASIC Bandwidth Scaling
Thermal Management in Packages
Data Center Network Topologies

Concept Map

Hinglish (regional understanding)

Intuition Hinglish mein samjho

Dekho, aajkal switch chips ka bandwidth bahut fast badh raha hai — 12.8, 25.6, 51.2 Tb/s aur aage. Problem ye hai ki data ko chip se nikalke faceplate tak (~20 cm copper trace) le jaana bahut mehenga pad raha hai. Copper par signal ka loss length aur frequency ke saath badhta hai, isliye jitna lamba raasta, utni zyada equalization aur utni zyada power (pJ per bit). Total power $P = E_b \times B$ hoti hai, aur 51.2 Tb/s par ye ~256 W tak pahunch jaata hai sirf I/O ke liye — ye sustainable nahi hai.

Co-packaged optics (CPO) ka simple funda: optical engine (jo bits ko light mein convert karta hai) ko faceplate se hata ke seedha ASIC ke bagal mein, same package par rakh do. Ab electrical signal ko sirf 1–5 mm chalna hai, faceplate tak nahi. Kam reach matlab kam loss matlab chhota, low-power SerDes. Ek idealized example mein $E_b$ 5 se 1 pJ/bit girta hai, jo 256 W se 51.2 W (~80% cut) dikhata hai — lekin ye sirf SerDes-reach wala portion hai. Real, poore link ka saving zyada modest hota hai, roughly 30–50%, kyunki modulators, TIA, thodi DSP aur laser ki efficiency bhi power leti hai.

Lekin free lunch nahi hai. CPO ka bada nuksaan: serviceability. Pluggable module kharab ho to bas nikaal ke naya lagao. CPO mein optics package ke andar sealed hai — ek engine fail hua to poora switch scrap ho sakta hai. Isliye laser ko aksar bahar rakhte hain (External Laser Source), kyunki laser sabse zyada fail hone wala aur temperature-sensitive part hai. Aur biggest headache: thermal — silicon photonics ke ring modulators temperature ke saath drift karte hain, aur inhe ekdum hot ASIC ke bagal mein rakhna padta hai.

Isliye industry hedge kar rahi hai: LPO/LRO (Linear Pluggable/Receive Optics) DSP hata dete hain par pluggable form factor rakhte hain — matlab zyada power saving ke saath serviceability ka risk kam. Exam/interview ke liye yaad rakho: CPO = same package (not same die), motivation = SerDes power aur copper loss, formula $P=E_b B$ , realistic saving ~30–50%, aur trade-off = serviceability + thermal.

WHAT is Co-packaged Optics?

WHY do we need it? (Derive the pressure from first principles)

HOW is CPO built?

The trade-offs (steel-man the objections)

Trends timeline (the numbers to remember)

Flashcards

Connections

Concept Map

Hinglish (regional understanding)

Go deeper — visual, from zero

Test yourself — Advanced & Emerging Architectures

Connections