Advanced & Emerging Architectures

Question 1 (10 marks)

(a) Bandwidth derivation (5)

• Bits per transfer per channel = 128 bits. (1)
• Transfers/s per pin = 2.0 GT/s; all 128 lanes transfer together → per channel = $128 \times 2.0\times10^9 = 256\times10^9$ bits/s. (1)
• 8 channels: $8 \times 256\times10^9 = 2.048\times10^{12}$ bits/s. (1)
• Convert to bytes: $\div 8 = 256\times10^9$ bytes/s $= 256$ GB/s. (1)
• Clear unit reasoning shown. (1)

Peak per stack = 256 GB/s.

(b) (2) 4 stacks → $4 \times 256 = 1024$ GB/s = 1.024 TB/s. (2)

(c) (3) HBM stacks DRAM dies vertically and connects them via a very wide bus (1024 bits/stack) over a short silicon interposer (2.5D) (1). The short, dense wiring supports thousands of I/O without long PCB traces, so bandwidth = width × rate is huge even at modest per-pin speed (1); lower per-pin frequency also reduces power and signal-integrity issues vs GDDR's high-frequency narrow bus (1).

Question 2 (12 marks)

(a) (5)

• Weight-stationary systolic array: data streams through PEs. (1)
• Model: latency to fill pipeline diagonally = $2N-1$ (or $N + N -1$) cycles for the wavefront to traverse. (1)
• To push all $M$ rows of activations through: total ≈ $M + 2N - 1$ cycles (fill + stream + drain). (1)
• With $M=N=256$: $256 + 2(256) - 1 = 256 + 511 = 767$ cycles. (1)
• Accept $\approx 3N-1 = 767$. Stated latency model clearly. (1)

Cycles ≈ 767.

(b) (4)

• Peak MACs = number of PEs × clock = $256^2 \times 700\times10^6$. (2)
• $= 65536 \times 7\times10^8 = 4.587\times10^{13}$ MAC/s. (1)
• ≈ 45.9 TMAC/s (≈ 91.8 TOPS counting mul+add). (1)

(c) (3) Weights are pre-loaded and held stationary in each PE (1); only activations flow in and partial sums accumulate along columns, so each weight is fetched once from memory instead of per-MAC (1), drastically cutting off-chip memory bandwidth and energy (data reuse) (1).

Question 3 (10 marks)

(a) (4) Amdahl: $S = \dfrac{1}{(1-f) + f/s}$ (2) $= \dfrac{1}{0.15 + 0.85/20} = \dfrac{1}{0.15 + 0.0425} = \dfrac{1}{0.1925} \approx 5.19\times$. (2)

(b) (2) $s\to\infty$: $S_{max} = 1/(1-f) = 1/0.15 \approx 6.67\times$. (2)

(c) (4)

• Original kernel time = 50 µs; accelerated compute = $50/20 = 2.5$ µs (1).
• Add 12 µs overhead → effective time = $2.5 + 12 = 14.5$ µs (1).
• Effective kernel speedup = $50 / 14.5 \approx 3.45\times$ (2).

Question 4 (10 marks)

(a) (6) Pseudocode (4) + annotation (2):

approx_add(A, B, k, n):        # n-bit operands, low k bits exact
    low  = (A & mask(k)) + (B & mask(k))   # exact ripple carry, k bits
    carry_in = low >> k                    # real carry out of low part
    highA = A >> k
    highB = B >> k
    # APPROXIMATION: drop cross-block carry chain in upper bits
    high = highA + highB + carry_in        # (or drop carry_in for more approx)
    return (high << k) | (low & mask(k))

• Larger $k$ → more exact bits → higher accuracy, higher energy/latency. (1)
• Smaller $k$ / dropped carry → shorter critical path, lower power, larger error. (1)

(b) (4) If carry propagation into the top 4 bits is truncated (carry dropped), a suppressed carry entering bit position 4 has weight $2^4 = 16$ (2). Worst case each dropped carry loses that weight; with truncation of the carry into the upper 4-bit block the max absolute error is the missing carry of weight $2^4$, i.e. 16 (2). (Accept reasoning giving $2^{k}=16$ where k=4.)

Question 5 (10 marks)

(a) (4) 3D/TSV stacks dies vertically → highest interconnect density and shortest wires → lowest latency and highest bandwidth (2), but stacked dies concentrate power in a small volume → severe thermal density / hotspot problem, hard to cool (1). 2.5D places dies side-by-side on an interposer → longer horizontal links (higher latency than 3D) but heat spreads laterally → easier thermal management (1).

(b) (3) PIM attacks the von Neumann bottleneck — the data-movement cost between separate memory and compute (1) — by putting compute inside/near memory arrays (1). Constraint: DRAM's specialized capacitor process is not logic-optimized, so few/slow transistors can be integrated, limiting logic complexity (also thermal/area) (1).

(c) (3) A full wafer inevitably has fabrication defects; without redundancy yield would be ~0 (1). WSEs include spare cores/links (1) and a reconfigurable interconnect/routing fabric that maps out defective tiles and reroutes traffic so the working fabric appears uniform (1).

Question 6 (8 marks)

(a) (3) Use the custom-0/custom-1 opcode space reserved in the RISC-V base ISA for non-standard extensions (2); these encodings are guaranteed never to be assigned to standard extensions, avoiding forward-compatibility collisions (1).

(b) (5)

macsat rd, rs1, rs2:
    prod   ← sext(rs1[31:0]) * sext(rs2[31:0])   # 64-bit signed product
    acc    ← sext(rd) + prod                     # accumulate
    if acc >  (2**31 - 1): rd ← 2**31 - 1         # saturate high
    elif acc < -(2**31):   rd ← -(2**31)          # saturate low
    else:                  rd ← acc[31:0]

• Signed multiply (1), accumulate into rd (1), high saturation to $2^{31}-1$ (1), low saturation to $-2^{31}$ (1), else write low 32 bits (1).

[
  {"claim":"HBM2 single stack peak bandwidth is 256 GB/s","code":"bits_per_transfer=128; rate=2.0e9; channels=8; bw_bits=bits_per_transfer*rate*channels; bw_GB=bw_bits/8/1e9; result = abs(bw_GB-256)<1e-6"},
  {"claim":"4 stacks give 1.024 TB/s","code":"per_stack_GB=256; total_TB=4*per_stack_GB/1000; result = abs(total_TB-1.024)<1e-9"},
  {"claim":"Systolic array cycles = 767 for N=M=256","code":"N=256; M=256; cycles=M+2*N-1; result = cycles==767"},
  {"claim":"Peak MACs approx 4.587e13","code":"pes=256**2; clk=700e6; macs=pes*clk; result = abs(macs-4.587e13)/4.587e13 < 0.001"},
  {"claim":"Amdahl speedup approx 5.19","code":"f=Rational(85,100); s=20; S=1/((1-f)+f/s); result = abs(float(S)-5.194805)<1e-3"},
  {"claim":"Max speedup approx 6.667","code":"f=Rational(85,100); Smax=1/(1-f); result = abs(float(Smax)-6.66667)<1e-3"},
  {"claim":"Effective kernel speedup with overhead approx 3.45","code":"orig=50; comp=orig/20; eff=comp+12; sp=orig/eff; result = abs(sp-3.44827586)<1e-3"},
  {"claim":"Max absolute error for dropped carry at bit 4 is 16","code":"k=4; err=2**k; result = err==16"}
]