Level 4 — ApplicationAdvanced & Emerging Architectures

Advanced & Emerging Architectures

⏱ 60 minutes60 marksprintable — key stays hidden on paper

Level: 4 (Application — novel/unseen problems, no hints) Time limit: 60 minutes Total marks: 60

Answer all questions. Show all reasoning. Use $...$ / $...$ for mathematical work. State assumptions where needed.

Question 1 — Chiplet Yield & Cost Economics (12 marks)

A vendor can build a large SoC either as (a) one monolithic die of area $600\ \text{mm}^2$ , or (b) four identical chiplets of $150\ \text{mm}^2$ each, integrated on a passive silicon interposer.

Assume defect density $D_0 = 0.10\ \text{defects/cm}^2$ and use the negative-binomial yield model with clustering parameter $\alpha = 3$ : $Y = \left(1 + \frac{A \cdot D_0}{\alpha}\right)^{-\alpha}$ where $A$ is die area in $\text{cm}^2$ .

(a) Compute the die yield $Y$ for the monolithic die and for a single chiplet. (4)

(b) A known-good-die (KGD) test screens chiplets before assembly. If interposer + assembly adds a combined yield of $0.95$ and the 4 chiplets are integrated only if all 4 are good, compute the effective assembly yield of the multi-die product (assume KGD guarantees each integrated chiplet is good, but the assembly step itself has yield $0.95$ ). (3)

(c) Given monolithic wafer cost yields effectively $\text{cost}_{mono} = \dfrac{C_{die}}{Y_{mono}}$ and the chiplet product cost is $\dfrac{4\,C_{chip}}{Y_{chip}} + C_{interposer}$ , with $C_{die}=C_{unit}\times 6$ , $C_{chip}=C_{unit}\times 1.5$ , $C_{interposer}=C_{unit}\times 2$ , and assembly yield from (b) applied to the whole chiplet product cost, determine which option is cheaper (express in units of $C_{unit}$ ). (3)

(d) State two non-cost technical drivers (besides yield) that motivate chiplet disaggregation. (2)

Question 2 — HBM Bandwidth & Systolic Array Sizing (14 marks)

A domain-specific accelerator pairs an HBM3 stack with a TPU-style systolic array (weight-stationary MAC grid).

HBM3 stack facts: 16 channels, each channel 64 bits wide, running at $6.4\ \text{Gbit/s}$ per pin.

(a) Compute the peak memory bandwidth of the single HBM3 stack in GB/s (use $1\ \text{GB} = 10^9$ bytes). (3)

(b) The systolic array is a square $N \times N$ grid clocked at $1\ \text{GHz}$ ; each PE does one MAC (2 FLOP) per cycle. Find the smallest $N$ (multiple of 32) whose peak throughput reaches at least $50\ \text{TFLOP/s}$ . (3)

(c) For that $N$ , compute the array's arithmetic intensity requirement (FLOP per byte) to stay compute-bound given the bandwidth from (a). (3)

(d) A $256\times256$ matrix multiply $C = A\times B$ (all $256\times256$ , one byte/element) is streamed once. Compute its arithmetic intensity (FLOP/byte, count $2N^3$ FLOP). Is it compute-bound on this system? Justify against your (c) answer. (3)

(e) Explain in one or two sentences why weight-stationary dataflow reduces HBM traffic compared to a naïve no-reuse scheme. (2)

Question 3 — Approximate Computing Error Budget (10 marks)

A neural inference accelerator replaces exact 16-bit multipliers with an approximate multiplier that truncates the lower $k$ bits of each 16-bit operand before multiplication.

(a) If truncating each operand introduces a relative error bounded by $2^{-(16-k)}$ , and the product's relative error is approximately the sum of operand relative errors, write the product's worst-case relative error bound as a function of $k$ . (2)

(b) The design target requires product relative error $\le 1\%$ . Find the maximum integer $k$ satisfying this. (3)

(c) Truncating $k$ bits reduces multiplier energy by an empirical factor $E(k) = E_0 \cdot (1 - 0.045k)$ . Compute the percentage energy saving at the maximum $k$ from (b). (2)

(d) Give one architectural reason approximate computing is acceptable for DNN inference but unacceptable for a cryptographic (OpenTitan) hardware root of trust. (3)

Question 4 — Quantum & Photonic Interconnect Reasoning (12 marks)

(a) A quantum processor holds 12 physical qubits, each with single-qubit gate error $1\times10^{-3}$ . A circuit applies a depth-40 sequence where every qubit receives one gate per layer. Estimate the probability the whole run is error-free (assume independent errors). Comment on whether this scales to 1000 qubits at the same depth. (4)

(b) Surface-code error correction needs roughly $d^2$ physical qubits per logical qubit for code distance $d$ , suppressing logical error rate as $\propto (p/p_{th})^{(d+1)/2}$ . If $p/p_{th}=0.1$ and you need logical error $\le 10^{-9}$ , find the smallest odd $d$ , and the physical-qubit overhead per logical qubit. (4)

(c) A co-packaged optics link carries $32$ wavelengths (DWDM), each modulated at $50\ \text{Gbit/s}$ . Compute aggregate link bandwidth in Tbit/s, and give two reasons co-packaged optics is replacing electrical SerDes for high-bandwidth die-to-die links. (4)

Question 5 — Architecture Selection & Justification (12 marks)

For each workload below, select the single most appropriate architecture from this chapter and justify in 2–3 sentences (name the mechanism that makes it suited). Do not reuse an architecture.

Options: wafer-scale engine · FPGA · processing-in-memory (PIM) · neuromorphic chip · RISC-V with custom vector extension · TPU/systolic array.

(a) Training a single enormous transformer where inter-chip communication dominates and you want to eliminate off-package network hops. (3)

(b) An always-on, battery-powered edge sensor doing sparse, event-driven pattern spotting at microwatts. (3)

(c) A protocol that changes every 6 months in a telecom base station, requiring hardware reconfiguration in the field. (3)

(d) A memory-bound graph analytics kernel where data movement, not compute, is the bottleneck. (3)

End of paper.

Answer keyMark scheme & solutions

Question 1 (12 marks)

(a) Areas in cm²: mono $A=6.0$ , chiplet $A=1.5$ .

$Y_{mono} = \left(1 + \frac{6.0\times0.10}{3}\right)^{-3} = (1+0.2)^{-3} = 1.2^{-3} = 0.5787$

$Y_{chip} = \left(1 + \frac{1.5\times0.10}{3}\right)^{-3} = (1+0.05)^{-3} = 1.05^{-3} = 0.8638$

Why: smaller die area → lower defect probability → higher yield. (2 marks each = 4)

(b) With KGD, each integrated chiplet is good by construction; the only loss is the assembly step. Effective assembly yield = $0.95$ . (Independent step; no compounding of chiplet die yields since KGD screens them.) (3) — full marks for recognising KGD removes the $Y_{chip}^4$ penalty and yield = 0.95.

(c) Monolithic: $\text{cost}_{mono} = \frac{6}{0.5787} = 10.37\ C_{unit}$

Chiplet product (4 good chiplets each costing $C_{chip}/Y_{chip}$ , plus interposer, all divided by assembly yield): $\text{cost}_{chip} = \frac{\dfrac{4\times1.5}{0.8638} + 2}{0.95} = \frac{6.945 + 2}{0.95} = \frac{8.945}{0.95} = 9.42\ C_{unit}$

Chiplet option is cheaper ( $9.42 < 10.37$ ). (3)

(d) Any two: mix process nodes (analog/IO on mature node, logic on leading node); reuse/modularity across product lines; larger effective silicon area beyond reticle limit; independent scaling of memory vs compute. (2)

Question 2 (14 marks)

(a) Total pins = $16 \times 64 = 1024$ bits. Bandwidth = $1024 \times 6.4\times10^9$ bit/s $= 6.5536\times10^{12}$ bit/s $= 819.2$ GB/s.

$\frac{1024 \times 6.4\times10^9}{8 \times 10^9} = 819.2\ \text{GB/s}$ (3)

(b) Throughput $= N^2 \times 2 \times 10^9$ FLOP/s. Need $\ge 50\times10^{12}$ : $N^2 \ge \frac{50\times10^{12}}{2\times10^9} = 25000 \Rightarrow N \ge 158.1$ Smallest multiple of 32 $\ge 158.1$ is $N=160$ . Peak $=160^2\times2\times10^9 = 51.2$ TFLOP/s. ✓ (3)

(c) To be compute-bound, required AI $\ge$ (peak FLOP/s) / (bandwidth): $\text{AI} \ge \frac{51.2\times10^{12}}{819.2\times10^{9}} = 62.5\ \text{FLOP/byte}$ (3)

(d) FLOP $= 2N^3 = 2\times256^3 = 33{,}554{,}432$ . Bytes moved (stream once, 3 matrices $256\times256$ × 1 byte) $= 3\times65536 = 196608$ . $\text{AI} = \frac{33554432}{196608} = 170.67\ \text{FLOP/byte}$ $170.67 > 62.5$ → compute-bound. (3)

(e) Weight-stationary keeps each weight resident in its PE and reuses it across many input activations, so weights are fetched from HBM once rather than per-MAC — cutting DRAM traffic by the reuse factor and shifting AI up. (2)

Question 3 (10 marks)

(a) Two operands each $2^{-(16-k)}$ ; product rel error $\approx 2\cdot2^{-(16-k)} = 2^{-(15-k)}$ . (2)

(b) Require $2^{-(15-k)} \le 0.01$ : $-(15-k)\ln2 \le \ln 0.01 \Rightarrow 15-k \ge \frac{\ln 100}{\ln 2} = 6.644 \Rightarrow k \le 8.356$ Max integer $k = 8$ . (Check: $2^{-7}=0.0078 \le 0.01$ ✓; $k=9 \Rightarrow 2^{-6}=0.0156 >0.01$ ✗.) (3)

(c) $E(8)=E_0(1-0.045\times8)=E_0(1-0.36)=0.64E_0$ . Saving $=36\%$ . (2)

(d) DNN inference is statistically robust: small per-MAC errors average out and the network's decision boundary tolerates noise, so accuracy is nearly unchanged. A crypto root of trust must be bit-exact and deterministic — any single flipped bit breaks integrity/authentication and could leak keys or forge signatures; there is no "acceptable error budget." (3)

Question 4 (12 marks)

(a) Gates per run $= 12 \times 40 = 480$ . Error-free prob $=(1-10^{-3})^{480} = 0.999^{480} \approx e^{-0.48} = 0.619$ (≈62%). For 1000 qubits, depth 40: $40000$ gates, $(0.999)^{40000}\approx e^{-40}\approx 4\times10^{-18}$ — essentially never error-free; NISC-scale circuits demand error correction. (4)

(b) Suppress $(0.1)^{(d+1)/2} \le 10^{-9}$ : $\frac{d+1}{2}\ge 9 \Rightarrow d \ge 17$ Smallest odd $d=17$ . Overhead $=d^2=289$ physical qubits per logical qubit. (4)

(c) Aggregate $=32\times50\ \text{Gbit/s} = 1600\ \text{Gbit/s} = 1.6\ \text{Tbit/s}$ . Reasons (any two): far lower energy/bit at high reach; no frequency-dependent copper channel loss/reach limit; higher bandwidth density (many wavelengths per fiber); reduced crosstalk and escape/pin limits vs electrical SerDes. (4)

Question 5 (12 marks) — model answers (3 each)

(a) Wafer-scale engine — the entire model fabric lives on one wafer, so cross-chip communication becomes on-wafer high-bandwidth low-latency mesh, eliminating off-package network hops and their bottleneck.

(b) Neuromorphic chip — event-driven spiking computation is active only when spikes occur, giving microwatt-class sparse pattern spotting; ideal for always-on edge sensing.

(c) FPGA — field-reconfigurable fabric lets the base-station hardware be reprogrammed for a new protocol every 6 months without silicon respin.

(d) Processing-in-memory (PIM) — compute is placed in/near the memory arrays, eliminating most data movement across the memory bus; directly attacks the bottleneck of a memory-bound graph kernel.

(TPU/systolic array and RISC-V vector remain unused — acceptable, since each option is used once and dense-matmul / general programmable-vector workloads aren't the best fit here.)

[
  {"claim":"Monolithic die yield = 1.2^-3 ≈ 0.5787","code":"Y=(1+ (6.0*0.10)/3)**(-3); result = abs(float(Y)-0.5787) < 1e-3"},
  {"claim":"Chiplet cost 9.42 < monolithic cost 10.37","code":"Ym=(1.2)**(-3); Yc=(1.05)**(-3); cm=6/Ym; cc=((4*1.5/Yc)+2)/0.95; result = bool(cc < cm and abs(float(cc)-9.42)<0.05)"},
  {"claim":"HBM3 stack bandwidth = 819.2 GB/s","code":"bw=(16*64*6.4e9)/8/1e9; result = abs(bw-819.2) < 1e-6"},
  {"claim":"256-cube matmul AI = 170.667 FLOP/byte and compute-bound (>62.5)","code":"ai=(2*256**3)/(3*256*256); result = bool(abs(float(ai)-170.6667)<1e-2 and ai>62.5)"},
  {"claim":"Approx multiplier max k = 8 for <=1% product error","code":"import sympy as sp; k=sp.symbols('k'); vals=[kk for kk in range(0,16) if 2**(-(15-kk)) <= 0.01]; result = (max(vals)==8)"},
  {"claim":"Surface code smallest odd d = 17 for logical error <=1e-9 at p/pth=0.1","code":"ds=[d for d in range(1,40,2) if (0.1)**((d+1)/2) <= 1e-9]; result = (min(ds)==17 and 17**2==289)"}
]