6.5.18 · D5Advanced & Emerging Architectures
Question bank — Co-packaged optics trends
The tools you need are all built in the parent: energy-per-bit (in pJ/bit, joules of energy spent to send one bit), aggregate bandwidth (bits per second), interface power , and channel loss growing with reach length and frequency . If any of those feel shaky, revisit the parent before scoring yourself here.
True or false — justify
Every claim below is stated as if true. Decide, then justify — the justification is the whole point.
CPO puts the optical engine on the same silicon die as the switch ASIC.
False. Co-packaged means same package/substrate with side-by-side chiplets; putting optics in the logic die is monolithic integration, a later and harder step. See 2.5D and 3D Packaging.
The main power win of CPO comes from making the lasers more efficient.
False. The win comes from shortening the electrical reach (cm → mm), which lets you use a tiny low-power SerDes; laser wall-plug efficiency is largely unchanged and is one reason whole-link saving stays at ~30–50%, not 80%.
Because is linear in , switch I/O power grows only linearly with bandwidth.
False. itself rises as line rate climbs (more channel loss → more equalization), so with both and increasing, grows super-linearly with capacity. That super-linear pressure is the real reason CPO exists.
Channel attenuation in dB grows with the square of trace length.
False. Attenuation is , linear in length . That linearity is exactly why chopping reach from ~20 cm to a few mm gives a proportional, dramatic dB-budget cut.
CPO is more field-serviceable than pluggables because everything sits neatly in one package.
False, backwards. A dead pluggable is a hot-swap; a dead co-packaged engine can mean scrapping a large sub-assembly or the whole switch. Integration costs you serviceability.
Linear Pluggable Optics (LPO) and CPO are the same idea.
False. LPO keeps the pluggable form factor but removes the DSP retimer to save power; CPO physically relocates the optics onto the ASIC package. LPO is the lower-risk hedge that captures much of the power win without losing modularity.
An External Laser Source (ELS) is used mainly to save cost on the laser.
False. The ELS lives outside the hot package chiefly for reliability and serviceability — lasers are the most temperature-sensitive, failure-prone part, so keeping them swappable offsets CPO's loss of field service.
The realistic headline power saving to quote for CPO is ~80%.
False. ~80% is only the idealized SerDes-reach slice ( pJ/bit in the parent example). The honest whole-link headline is ~30–50%, because modulators, TIAs, residual DSP, and laser inefficiency all remain.
Spot the error
Each statement contains one flaw. Name it.
"Skin-effect loss scales with , so doubling frequency doubles that term."
The error: skin loss scales with , not . In , the term is skin effect and the term is dielectric loss; doubling raises skin loss by only .
"With CPO the electrical reach is zero millimeters, so can reach zero pJ/bit."
Two errors: CPO reach is a few mm, not zero (that's monolithic optical I/O), and has a nonzero floor — drivers, modulators, and TIAs always burn energy. The parent targets ~1 pJ/bit, not 0.
"Because CPO removes faceplate pluggables, you can no longer mix reaches or speeds per port."
The consequence is real but stated as if it were a benefit-free fact. Loss of per-port reach/speed flexibility is a genuine trade-off/drawback, which is precisely why hyperscalers hedge with LPO/LRO rather than going all-CPO.
"On-board optics (OBO) requires ~1–5 mm of electrical reach, same as CPO."
The error: OBO sits near the ASIC on the PCB and needs ~5–10 cm; only CPO on the package gets down to ~1–5 mm. OBO is the interim step between pluggable and co-packaged.
"The 256 W in the parent example is the total power of a 51.2 Tb/s switch."
The error: 256 W is only the electrical I/O interface power at 5 pJ/bit — it sits on top of the switch core and optics power, not instead of them.
Why questions
Reason it through in one or two sentences.
Why does moving to 224 Gb/s per lane, versus 112 Gb/s, "break" copper reach so sharply?
Higher line rate means higher signalling frequency, and both loss terms () climb, so over the same trace the equalizer must recover far more dB — beyond a point no practical DSP closes the link, forcing optics closer. See Switch ASIC Bandwidth Scaling.
Why is thermal management the "central engineering headache" of CPO specifically?
Optics are temperature-sensitive — ring resonators drift and lasers redshift with heat — yet CPO deliberately co-locates them beside a hot power-hungry ASIC, so you must cool sensitive optics right next to the biggest heat source. See Thermal Management in Packages.
Why does shortening electrical reach let you use a smaller SerDes, not just a cooler one?
A short, low-loss channel needs far less equalization (less CTLE/DFE/FFE) and re-clocking, so you can drop circuitry entirely — the SerDes shrinks in area and complexity, not merely in wattage.
Why does the industry pursue LPO/LRO alongside CPO instead of committing to one?
They hedge risk: LPO/LRO grab most of the power win (removing DSP) while keeping the serviceable, modular pluggable form factor, so they're a lower-risk bridge while CPO's manufacturing and service model matures.
Why does CPO free faceplate area and reduce retimer chips, beyond the pJ/bit story?
With optics off the faceplate you're no longer limited by front-panel connector density, boosting lane density, and short clean links eliminate mid-path retimers — system-level wins the raw energy-per-bit figure never captures. Relevant to Data Center Network Topologies.
Why is Silicon Photonics the enabler rather than exotic III–V optics for the whole engine?
Silicon photonics builds waveguides, modulators, and detectors in CMOS-compatible processes, giving wafer-scale, cheap, integrable optics that can sit on the shared substrate — exactly what co-packaging demands.
Edge cases
Boundary and degenerate scenarios — where a naive rule quietly fails.
At the limit of zero electrical reach (), does interface power go to zero?
No. removes channel loss, but still has a floor from drivers, modulators, TIAs and laser inefficiency, so stays well above zero. That limit is optical I/O, still not free.
If a design keeps pluggable form factor but deletes the DSP retimer, is that CPO?
No — that's LPO (or LRO on the receive side). It captures power savings without relocating optics onto the package, so it's a different point on the integration spectrum.
What happens to CPO's power argument if channel loss were somehow flat (frequency-independent)?
The super-linear pressure would largely vanish — would stop rising with line rate, so would grow roughly linearly and faceplate SerDes could scale much further, weakening the core motivation for CPO.
For a short-reach, low-rate link (e.g., chip-to-chip on one board), is CPO worth it?
Usually not. When reach is already small and rate modest, is tiny and cheap SerDes already suffices; CPO's serviceability cost isn't justified — it pays off only where reach × frequency loss is punishing.
When exactly does the naive "just add more DSP equalization" fix stop working?
When the recovered dB budget hits the point where equalizer power and latency balloon and residual noise/ISI floors error rate — you can't equalize an arbitrarily lossy channel, so past that reach×rate the only fix is shortening the link (CPO) or going optical. Ties into SerDes and Wireline Links.
If the External Laser Source itself fails in a CPO system, how does serviceability compare to the engine failing?
The ELS is deliberately kept outside the sealed package precisely so it can be swapped like a pluggable; a failure of the co-packaged engine inside is the non-serviceable case. The split exists to isolate the least-reliable part.
Recall One-line self-test before you leave
Name the three trade-offs CPO accepts for its power win. ::: Loss of field serviceability, loss of per-port modularity/mix-and-match, and a hard thermal problem from co-locating heat-sensitive optics with a hot ASIC.