Co-packaged optics trends: Exercises — Hardware deep dive

The only formula you truly need is the one from the parent note. Let us re-earn it from zero so nothing is assumed.

Two more tools we will use, defined before we touch them:

Level 1 — Recognition

L1.1

Which of these lives on the same package substrate as the switch ASIC in a CPO design: (a) a QSFP-DD faceplate module, (b) the optical engine, (c) the External Laser Source?

Recall Solution

Answer: (b) the optical engine. By definition, co-packaged optics places the optical engine (modulators + photodetectors + short-reach SerDes/driver) on the same package as the ASIC. A QSFP-DD sits at the faceplate (that is exactly what CPO removes). The External Laser Source (ELS) is deliberately kept outside the hot package so a failed laser can be swapped — so it is not on the package. Only (b) qualifies.

L1.2

Order these by electrical reach, shortest first: Pluggable, On-board optics (OBO), Co-packaged optics.

Recall Solution

Shortest → longest: CPO ( $\sim$ 1–5 mm) < OBO ( $\sim$ 5–10 cm) < Pluggable ( $\sim$ 10–30 cm). The whole point of the integration spectrum is that moving optics closer to the die shrinks the electrical journey. CPO is the shortest of these three (only monolithic optical I/O, at $\sim$ 0, is shorter).

L1.3

Convert $5 pJ/bit$ into joules per bit. Convert $51.2 Tb/s$ into bits per second.

Recall Solution

$5 pJ/bit = 5 \times 1 0^{- 12} J/bit$ (because "pico" = $1 0^{- 12}$ ). $51.2 Tb/s = 51.2 \times 1 0^{12} bit/s$ (because "tera" = $1 0^{12}$ ). These are the two numbers you will drop straight into $P = E_{b} \times B$ next level.

Level 2 — Application

L2.1

A 51.2 Tb/s switch uses faceplate SerDes at $E_{b} = 5 pJ/bit$ . Compute the electrical-interface power $P$ .

Recall Solution

$P = E_{b} \times B = (5 \times 1 0^{- 12} \frac{J}{bit}) \times (51.2 \times 1 0^{12} \frac{bit}{s}) .$ Multiply the mantissas: $5 \times 51.2 = 256$ . Multiply the powers of ten: $1 0^{- 12} \times 1 0^{12} = 1 0^{0} = 1$ . $P = 256 W .$ What it means: 256 W just for electrical I/O, on top of the switch core — the "SerDes tax" the parent note warns about.

L2.2

Same switch, but CPO shrinks the reach so $E_{b} = 1 pJ/bit$ . Compute $P$ and the fractional saving vs. L2.1.

Recall Solution

$P = (1 \times 1 0^{- 12}) \times (51.2 \times 1 0^{12}) = 51.2 W .$ Saving $= \frac{256 - 51.2}{256} = \frac{204.8}{256} = 0.8 = 80%$ . Read carefully: this 80% is only the SerDes-reach portion under this idealized $5 \to 1$ assumption. Whole-link saving is a more honest 30–50% (see L2's trap).

L2.3

Bandwidth doubles to 102.4 Tb/s. At the same CPO $E_{b} = 1 pJ/bit$ , what is $P$ ?

Recall Solution

$P = (1 \times 1 0^{- 12}) \times (102.4 \times 1 0^{12}) = 102.4 W .$ Because $P = E_{b} B$ is linear in $B$ at fixed $E_{b}$ , doubling bandwidth exactly doubles power ( $51.2 \to 102.4$ W). The scary part the parent note flags is that in the real world $E_{b}$ also rises with line rate, so power grows faster than this clean doubling.

L2.4

A copper trace has loss $α = 1.2 dB/cm$ at the operating frequency. Faceplate reach is $20 cm$ ; CPO reach is $0.3 cm$ (3 mm). Compute both dB budgets and the reduction.

Recall Solution

Use $A = α \cdot L$ (loss is linear in length). Faceplate: $A = 1.2 \times 20 = 24 dB$ . CPO: $A = 1.2 \times 0.3 = 0.36 dB$ . The equalizer must recover $24 dB$ vs only $0.36 dB$ — a $\sim 66 \times$ smaller budget. That is why CPO can use a tiny, low-power SerDes: there is almost nothing to equalize.

Level 3 — Analysis

L3.1

Two designs move the same 51.2 Tb/s: (A) faceplate at $5 pJ/bit$ , (B) LPO that removes the DSP and reaches $2.5 pJ/bit$ while keeping the pluggable form factor. Compute B's power, its saving vs A, and argue when you'd pick B over full CPO.

Recall Solution

$P_{B} = (2.5 \times 1 0^{- 12}) \times (51.2 \times 1 0^{12}) = 128 W .$ Saving vs A: $\frac{256 - 128}{256} = 50%$ . Analysis: LPO captures half the link power (vs CPO's idealized 80% SerDes-slice) but keeps the pluggable form factor — so you retain field serviceability and per-port reach/speed mixing. Pick LPO when serviceability and modularity matter more than the last increment of power; pick CPO when you are power/faceplate-limited and can accept a sealed, non-serviceable switch.

L3.2

The parent note says loss grows like $α (f) = a f + b f$ . At low frequency which term dominates, and at very high frequency which? What does that imply as lanes move 112 → 224 Gb/s?

Recall Solution

Compare growth rates. For small $f$ , $f$ (skin effect) is larger than $f$ (dielectric), so the skin-effect term $a f$ dominates. As $f$ grows, the linear $b f$ term eventually overtakes $f$ (a line beats a square-root), so the dielectric term $b f$ dominates at very high frequency. Implication: doubling the lane rate $112 \to 224$ Gb/s pushes the signal energy up in frequency where the fast-growing dielectric term rules — loss climbs disproportionately. That is precisely "where copper reach really breaks," motivating CPO / short-reach SerDes.

L3.3

A ring-modulator resonance drifts $\sim 0.1 nm /^{\circ} C$ . If co-locating on the hot ASIC raises the optics temperature by $30^{\circ} C$ , how far does resonance drift, and why is this the central CPO headache?

Recall Solution

Drift $= 0.1 \frac{nm}{^{\circ} C} \times 30^{\circ} C = 3 nm$ . A ring only passes light near its resonant wavelength; a 3 nm shift can move it off the laser's channel entirely, killing the link. Faceplate optics sit in cool, controlled air; CPO glues the optics to a die dumping hundreds of watts. That is why thermal management (and keeping the laser external) is the make-or-break engineering problem — not the pJ/bit math, which is the easy part.

Level 4 — Synthesis

L4.1

Build a total-power model. A 51.2 Tb/s switch has core power $P_{core} = 300 W$ . Case A: faceplate I/O at $5 pJ/bit$ . Case C: CPO I/O at $1 pJ/bit$ . Compute total power each case and the system-level saving (not just the I/O slice). Then explain why the honest headline is smaller than 80%.

Recall Solution

I/O powers (from L2): $P_{IO,A} = 256 W$ , $P_{IO,C} = 51.2 W$ . Totals: $P_{A} = 300 + 256 = 556 W, P_{C} = 300 + 51.2 = 351.2 W .$ System saving $= \frac{556 - 351.2}{556} = \frac{204.8}{556} \approx 0.368 = 36.8%$ . Synthesis point: the same absolute 204.8 W saving is 80% of the I/O slice but only ~37% of the total, because the 300 W core is untouched. This is exactly why the parent note's honest headline is ~30–50% whole-system, not 80%.

L4.2

Sketch (as a Mermaid flow) the decision an architect makes among Pluggable, LPO, and CPO, driven by three factors: power budget, serviceability need, faceplate/density limit.

Recall Solution

flowchart TD
  A["Start: choose optics strategy"] --> B["Is power budget the hard limit"]
  B -->|no| C["Keep Pluggable QSFP-DD or OSFP"]
  B -->|yes| D["Must optics be field serviceable"]
  D -->|yes| E["Use LPO keep pluggable trim DSP"]
  D -->|no| F["Is faceplate density also limiting"]
  F -->|no| E
  F -->|yes| G["Go Co-packaged Optics sealed max density"]

Reading it: power pressure is the gate; if you also refuse to lose serviceability you land on LPO; only when you accept a sealed switch and need faceplate density does full CPO win. This encodes the L3.1 and L3.3 trade-offs into one path.

Level 5 — Mastery

L5.1

Design target: an architect wants total switch I/O power $\leq 60 W$ at $B = 102.4 Tb/s$ . What end-to-end $E_{b}$ (pJ/bit) must the optical I/O hit? Is that within the parent note's stated CPO targets? Defend the answer.

Recall Solution

Invert the engine: $E_{b} = \frac{P}{B}$ . $E_{b} = \frac{60 W}{102.4 \times 1 0 ^{12} bit/s} = 5.859 \times 1 0^{- 13} J/bit \approx 0.586 pJ/bit .$ Defence: the parent note's CPO target is < 5 pJ/bit end-to-end, aiming toward ~1 pJ/bit optical I/O. Requiring $\approx 0.59 pJ/bit$ is below even the ~1 pJ/bit aspiration — so this budget is more aggressive than current CPO goals. It's physically the right direction (short reach + silicon photonics) but demands better-than-state-of-the-art efficiency; the architect should either relax the budget toward ~100 W (giving ~1 pJ/bit) or wait for monolithic optical I/O.

L5.2

Mastery synthesis: at $B = 102.4 Tb/s$ , compare (i) faceplate 5 pJ/bit, (ii) LPO 2.5 pJ/bit, (iii) CPO 1 pJ/bit. Give each I/O power and each saving vs faceplate. Then state, in one sentence each, the non-power cost you accept moving down the list.

Recall Solution

Using $P = E_{b} \times 102.4 \times 1 0^{12}$ :

(i) Faceplate: $5 \times 1 0^{- 12} \times 102.4 \times 1 0^{12} = 512 W$ — baseline.
(ii) LPO: $2.5 \times 1 0^{- 12} \times 102.4 \times 1 0^{12} = 256 W$ → saving $\frac{512 - 256}{512} = 50%$ .
(iii) CPO: $1 \times 1 0^{- 12} \times 102.4 \times 1 0^{12} = 102.4 W$ → saving $\frac{512 - 102.4}{512} = 80%$ .

Non-power costs accepted going down:

Faceplate → LPO: you lose the safety of on-module DSP; the link now depends on the host SerDes equalizing a longer channel (a link-budget risk), but keep the pluggable body.
LPO → CPO: you lose field serviceability and modularity — the optics are sealed onto the package substrate, and a dead engine can mean scrapping the switch, while the hot ASIC now threatens optical thermal stability. Verdict: power savings and integration risk rise together; there is no free lunch, only a chosen point on the curve.

Recall One-line self-check

Why is the CPO whole-switch saving (~37% in L4.1) so much less than the I/O-slice saving (80%)? ::: Because the untouched switch core power sits in the denominator of the whole-switch percentage but not in the I/O-slice percentage — same joules saved, bigger base.

See also: Switch ASIC Bandwidth Scaling · Data Center Network Topologies · Co-packaged optics trends