Exercises — Co-packaged optics trends

Answer: (b) optical engine. Definition ke hisaab se, co-packaged optics optical engine ko (modulators + photodetectors + short-reach SerDes/driver) ASIC ke same package par rakhta hai. QSFP-DD faceplate par hota hai (yahi woh cheez hai jo CPO hataata hai). External Laser Source (ELS) ko jaanbujhkar hot package ke bahar rakha jaata hai taaki failed laser swap ki ja sake — isliye woh package par nahi hota. Sirf (b) qualify karta hai.

Chhota → bada: CPO ($\sim$1–5 mm) < OBO ($\sim$5–10 cm) < Pluggable ($\sim$10–30 cm). Integration spectrum ka poora point yahi hai ki optics ko die ke paas laane se electrical journey chhoti hoti hai. CPO in teeno mein sabse chhoti hai (sirf monolithic optical I/O, $\sim$0 par, aur chhoti hai).

$5\text{pJ/bit}=5\times 10^{-12}\text{J/bit}$ (kyunki "pico" = $10^{-12}$). $51.2\text{Tb/s}=51.2\times 10^{12}\text{bit/s}$ (kyunki "tera" = $10^{12}$). Yahi woh do numbers hain jo tum seedha $P=E_b\times B$ mein agle level par daaloge.

$P=E_b\times B=(5\times 10^{-12}\frac{\text{J}}{\text{bit}})\times (51.2\times 10^{12}\frac{\text{bit}}{\text{s}}).$ Mantissas multiply karo: $5\times 51.2=256$. Powers of ten multiply karo: $10^{-12}\times 10^{12}=10^0=1$. $P=256\text{W}.$ Iska matlab: sirf electrical I/O ke liye 256 W, switch core ke upar — woh "SerDes tax" jiske baare mein parent note warn karta hai.

$P=(1\times 10^{-12})\times (51.2\times 10^{12})=51.2\text{W}.$ Saving $=\frac{256-51.2}{256}=\frac{204.8}{256}=0.8=80\%$. Dhyan se padho: yeh 80% sirf SerDes-reach portion ke liye hai is idealized $5\to 1$ assumption ke under. Whole-link saving zyada honest 30–50% hai (L2 ka trap dekho).

$P=(1\times 10^{-12})\times (102.4\times 10^{12})=102.4\text{W}.$ Kyunki fixed $E_b$ par $P=E_{b}B$ $B$ mein linear hai, bandwidth double karne se power exactly double hoti hai ($51.2\to 102.4$ W). Parent note jo scary baat flag karta hai woh yeh hai ki real world mein $E_b$ bhi line rate ke saath badhta hai, toh power is clean doubling se zyada tez badhti hai.

$A=\alpha \cdot L$ use karo (loss length mein linear hai). Faceplate: $A=1.2\times 20=24\text{dB}$. CPO: $A=1.2\times 0.3=0.36\text{dB}$. Equalizer ko $24\text{dB}$ recover karna hai vs sirf $0.36\text{dB}$ — ek $\sim 66\times$ chhota budget. Isliye CPO ek tiny, low-power SerDes use kar sakta hai: equalize karne ke liye almost kuch hai hi nahi.

$P_B=(2.5\times 10^{-12})\times (51.2\times 10^{12})=128\text{W}.$ A se saving: $\frac{256-128}{256}=50\%$. Analysis: LPO link power ka half capture karta hai (vs CPO ka idealized 80% SerDes-slice) lekin pluggable form factor rakhta hai — isliye tum field serviceability aur per-port reach/speed mixing retain karte ho. LPO tab choose karo jab serviceability aur modularity power ke last increment se zyada matter kare; CPO tab choose karo jab tum power/faceplate-limited ho aur ek sealed, non-serviceable switch accept kar sako.

Growth rates compare karo. Chhote $f$ ke liye, $\sqrt{f}$ (skin effect) $f$ (dielectric) se bada hota hai, toh skin-effect term $a\sqrt{f}$ dominate karta hai. Jaise $f$ badhta hai, linear $bf$ term eventually $\sqrt{f}$ ko overtake kar leta hai (ek line ek square-root ko beat karti hai), toh very high frequency par dielectric term $bf$ dominate karta hai. Implication: lane rate $112\to 224$ Gb/s double karne se signal energy frequency mein upar jaati hai jahan tez badhne wala dielectric term rule karta hai — loss disproportionately badhti hai. Yahi hai "jahan copper reach sach mein toot ti hai," jo CPO / short-reach SerDes ko motivate karta hai.

Drift $=0.1\frac{\text{nm}}{{}^{\circ }\text{C}}\times 30{}^{\circ }\text{C}=3\text{nm}$. Ek ring sirf apni resonant wavelength ke paas light pass karta hai; ek 3 nm shift use laser ke channel se bahar move kar sakta hai, link ko kill karte hue. Faceplate optics cool, controlled air mein baithe hote hain; CPO optics ko ek aisi die se glue kar deta hai jo hundreds of watts dump karti hai. Isliye thermal management (aur laser ko external rakhna) woh make-or-break engineering problem hai — pJ/bit math nahi, jo easy part hai.

I/O powers (L2 se): $P_{\text{IO,A}}=256\text{W}$, $P_{\text{IO,C}}=51.2\text{W}$. Totals: $P_A=300+256=556\text{W},P_C=300+51.2=351.2\text{W}.$ System saving $=\frac{556-351.2}{556}=\frac{204.8}{556}\approx 0.368=36.8\%$. Synthesis point: wahi absolute 204.8 W saving I/O slice ka 80% hai lekin total ka sirf ~37%, kyunki 300 W core unchanged hai. Isliye parent note ka honest headline ~30–50% whole-system hai, 80% nahi.

flowchart TD
  A["Start: choose optics strategy"] --> B["Is power budget the hard limit"]
  B -->|no| C["Keep Pluggable QSFP-DD or OSFP"]
  B -->|yes| D["Must optics be field serviceable"]
  D -->|yes| E["Use LPO keep pluggable trim DSP"]
  D -->|no| F["Is faceplate density also limiting"]
  F -->|no| E
  F -->|yes| G["Go Co-packaged Optics sealed max density"]

Isko padhna: power pressure gate hai; agar tum serviceability bhi nahi kho sakte toh LPO par laandte ho; sirf tab jab tum ek sealed switch accept karte ho aur faceplate density bhi limit kar rahi ho tab full CPO jeetता hai. Yeh L3.1 aur L3.3 ke trade-offs ko ek path mein encode karta hai.

Engine invert karo: $E_b=\frac{P}{B}$. $E_b=\frac{60\text{W}}{102.4\times 10^{12}\text{bit/s}}=5.859\times 10^{-13}\text{J/bit}\approx 0.586\text{pJ/bit}.$ Defence: parent note ka CPO target hai < 5 pJ/bit end-to-end, ~1 pJ/bit optical I/O ki taraf aim karta hua. $\approx 0.59\text{pJ/bit}$ require karna ~1 pJ/bit aspiration se bhi neeche hai — toh yeh budget current CPO goals se bhi zyada aggressive hai. Yeh physically sahi direction hai (short reach + silicon photonics) lekin better-than-state-of-the-art efficiency demand karta hai; architect ko ya toh budget ~100 W tak relax karna chahiye (~1 pJ/bit deta hai) ya monolithic optical I/O ka wait karna chahiye.

$P=E_b\times 102.4\times 10^{12}$ use karke:

• (i) Faceplate: $5\times 10^{-12}\times 102.4\times 10^{12}=512\text{W}$ — baseline.
• (ii) LPO: $2.5\times 10^{-12}\times 102.4\times 10^{12}=256\text{W}$ → saving $\frac{512-256}{512}=50\%$.
• (iii) CPO: $1\times 10^{-12}\times 102.4\times 10^{12}=102.4\text{W}$ → saving $\frac{512-102.4}{512}=80\%$.

Neeche jaane par accept kiye gaye non-power costs:

• Faceplate → LPO: tum on-module DSP ki safety kho dete ho; link ab host SerDes par depend karta hai ek longer channel equalize karne ke liye (ek link-budget risk), lekin pluggable body reh jaati hai.
• LPO → CPO: tum field serviceability aur modularity kho dete ho — optics package substrate par seal ho jaati hain, aur ek dead engine ka matlab switch scrap karna ho sakta hai, jabki hot ASIC ab optical thermal stability ko threaten karta hai. Verdict: power savings aur integration risk saath-saath badhte hain; koi free lunch nahi hai, sirf curve par ek chosen point hai.

CPO whole-switch saving (~37% L4.1 mein) I/O-slice saving (80%) se itni kam kyun hai? ::: Kyunki untouched switch core power whole-switch percentage ke denominator mein baithta hai lekin I/O-slice percentage mein nahi — same joules saved, bada base.