Co-packaged optics trends: Worked examples — Hardware deep dive

Before anything, let us re-earn the two symbols so a newcomer never trips:

The scenario matrix

Every case this topic can throw at you falls into one of these cells. The examples below are labelled with the cell they hit, and together they fill every row.

Cell	What it stresses	Degenerate/limit?	Example
A. Baseline compute	Plug numbers into $P = E_{b} B$	no	Ex 1
B. Savings / ratio	Compare two $E_{b}$ values	no	Ex 2
C. Scope trap	80% vs 30–50% — right number for right scope	no	Ex 3
D. Zero / degenerate	$L \to 0$ , $E_{b} \to$ floor	yes	Ex 4
E. Loss law + length	$A = α (f) L$ , halve the reach	limiting in $L$	Ex 5
F. Frequency scaling	$α (f) = a f + b f$ , lane rate up	limiting in $f$	Ex 6
G. Real-world word problem	rack of switches, electricity bill	no	Ex 7
H. Exam twist	solve backwards for the $E_{b}$ target	inverse	Ex 8

Cell A — the baseline computation

Worked example Ex 1 (Cell A): interface power of a 51.2 Tb/s switch

A switch ASIC moves $B = 51.2 Tb/s$ over long-reach faceplate SerDes at $E_{b} = 5 pJ/bit$ . What is the electrical-interface power?

Forecast: guess — is it tens of watts, hundreds, or thousands? Write your guess.

Convert both numbers to base SI units. $E_{b} = 5 pJ/bit = 5 \times 1 0^{- 12} J/bit$ , and $B = 51.2 Tb/s = 51.2 \times 1 0^{12} bit/s$ . Why this step? The formula only gives watts if we feed joules and bits/s. Mixing pJ with Tb/s "hides" the cancellation and invites off-by- $1 0^{24}$ blunders.
Multiply. $P = (5 \times 1 0^{- 12}) \times (51.2 \times 1 0^{12}) = 5 \times 51.2 = 256 W$ Why this step? The $1 0^{- 12}$ and $1 0^{+ 12}$ cancel exactly — that is the whole reason pJ/bit and Tb/s are the natural units here: the exponents are engineered to annihilate.

Verify: units $= \frac{J}{bit} \cdot \frac{bit}{s} = W$ . ✓ Sanity: 256 W is roughly two bright desktop-PC power supplies — plausible for a whole rack-top switch's I/O alone, which is exactly why engineers panic.

Cell B — the savings ratio

Worked example Ex 2 (Cell B): how much does CPO save here?

Same switch. CPO shrinks the electrical reach to millimetres, letting $E_{b}$ fall from $5$ to $1 pJ/bit$ . Find the new power and the fractional saving.

Forecast: the ratio $5 \to 1$ — what fraction of the power disappears?

Recompute with the new $E_{b}$ . $P_{CPO} = (1 \times 1 0^{- 12}) (51.2 \times 1 0^{12}) = 51.2 W$ Why this step? $B$ is unchanged (same switch throughput), so only $E_{b}$ moves — a clean controlled comparison.
Take the fractional saving: $saving = \frac{P _{old} - P _{new}}{P _{old}} = \frac{256 - 51.2}{256} = \frac{204.8}{256} = 0.8 = 80%$ Why this step? A ratio removes the units and tells us the improvement independent of switch size — because $B$ cancels, an 80% cut holds for any $B$ as long as $E_{b}$ goes $5 \to 1$ .

Verify: $51.2 = 256/5$ , and $5 \to 1$ is exactly a factor of 5, so $1/5 = 20%$ remains, $80%$ gone. ✓ Ratio is dimensionless ✓.

Cell C — the scope trap (the number that fools people)

Worked example Ex 3 (Cell C): why the headline is 30–50%, not 80%

The parent note warns the 80% figure is only the SerDes-reach slice. Suppose the full link burns $256 W$ of SerDes-reach power plus a fixed $F = 120 W$ in modulators, TIAs, DSP-lite and laser inefficiency that CPO does not remove. What is the realistic whole-link saving?

Forecast: will it still be near 80%, or lower?

Old whole-link power: $P_{old} = 256 + 120 = 376 W$ . Why this step? "Whole-link" is a wider scope than "SerDes-reach". We must add the fixed floor $F$ that both technologies pay.
New whole-link power: the SerDes slice drops $256 \to 51.2$ , the floor stays. $P_{new} = 51.2 + 120 = 171.2 W$ . Why this step? CPO cannot delete the optical devices themselves — the pJ/bit floor is not zero, exactly as the parent note stresses.
Fractional saving: $\frac{376 - 171.2}{376} = \frac{204.8}{376} \approx 0.545 = 54.5%$ Why this step? Same absolute watts saved ( $204.8 W$ ) but divided by a bigger base → a smaller percentage. This is precisely why scope changes the headline.

Verify: absolute saving $204.8 W$ identical to Ex 2 ✓; $54.5% < 80%$ ✓ and it sits in the "30–50%-ish realistic" band once you add more floor. The lesson: quote 80% only for the SerDes portion.

Cell D — the zero / degenerate edge

Worked example Ex 4 (Cell D): what happens as reach

$\to 0$ ? Monolithic optical I/O pushes the electrical reach $L \to 0$ . Does the interface power also go to zero? Use $E_{b} (L) = E_{floor} + k L$ with a fixed floor $E_{floor} = 0.8 pJ/bit$ , slope $k = 0.14 pJ/bit per cm$ , on the same $51.2 Tb/s$ switch.

Forecast: does power fall to 0 W, or to some non-zero limit?

Model at $L = 30 cm$ (faceplate): $E_{b} = 0.8 + 0.14 (30) = 0.8 + 4.2 = 5.0 pJ/bit$ . Why this step? We tune the model so the faceplate case reproduces the known $5 pJ/bit$ — sanity-anchoring before extrapolating.
Take the limit $L \to 0$ : $lim_{L \to 0} E_{b} (L) = E_{floor} = 0.8 pJ/bit$ Why this step? As length vanishes the $k L$ term dies, but the floor survives — the driver, modulator and receiver still cost energy even with a wire of zero length.
So the limiting power is $P_{min} = (0.8 \times 1 0^{- 12}) (51.2 \times 1 0^{12}) = 40.96 W$ Why this step? This is the hard floor: no packaging trick beats it without changing the optical devices themselves.

Verify: at $L = 0$ , $E_{b} = 0.8$ ; $0.8 \times 51.2 = 40.96 W$ , which is not zero ✓. The degenerate case teaches the key truth: shrinking length gives diminishing returns toward a non-zero floor, never toward nothing.

Cell E — the loss law and length

Worked example Ex 5 (Cell E): copper budget, faceplate vs CPO

A copper channel at one lane rate has attenuation coefficient $α = 1.6 dB/cm$ (this already bakes in the frequency). Compare the loss the equalizer must recover for faceplate reach $L_{1} = 25 cm$ versus CPO reach $L_{2} = 0.5 cm$ .

Forecast: by roughly what factor does the dB budget shrink?

Faceplate loss: $A_{1} = α L_{1} = 1.6 \times 25 = 40 dB$ . Why this step? $A = α L$ is linear in length, so we just multiply — the geometry is a straight line through the origin (see figure).
CPO loss: $A_{2} = α L_{2} = 1.6 \times 0.5 = 0.8 dB$ . Why this step? Same coefficient, tiny length — the whole point of CPO is to slide left on that straight line.
Ratio of budgets: $A_{1} / A_{2} = 40/0.8 = 50$ . Why this step? Because loss is linear in $L$ , the loss ratio equals the length ratio $25/0.5 = 50$ . Linearity is what makes "shorten the wire" a direct dB win.

Verify: $L_{1} / L_{2} = 25/0.5 = 50 = A_{1} / A_{2}$ ✓. A 40 dB budget means the received signal is $1 0^{4}$ × weaker in power — brutal DSP; 0.8 dB is nearly free. The red dot on the figure sits near the origin: that's CPO.

Cell F — frequency scaling (limiting behaviour in $f$ )

Worked example Ex 6 (Cell F): why 224 Gb/s "breaks copper"

Loss per cm is $α (f) = a f + b f$ with $a = 0.10 \frac{dB}{cm GHz}$ (skin effect) and $b = 0.03 \frac{dB}{cm GHz}$ (dielectric). A PAM4 lane's key frequency is roughly (line-rate/4) in GHz. Compare $112 Gb/s$ (Nyquist $\approx 28 GHz$ ) with $224 Gb/s$ (Nyquist $\approx 56 GHz$ ) on a $10 cm$ trace.

Forecast: does doubling the rate roughly double the loss, or more than double?

At $f = 28 GHz$ : $α = 0.10 28 + 0.03 (28) = 0.10 (5.2915) + 0.84 = 0.52915 + 0.84 = 1.36915 dB/cm$ . Loss over $10 cm$ : $A_{28} = 13.69 dB$ . Why this step? We use $f$ for skin effect (current crowds to the wire's surface, worse with frequency) and linear $f$ for dielectric (the insulator soaks up more energy as it wiggles faster) — two different physics, hence two terms.
At $f = 56 GHz$ : $α = 0.10 56 + 0.03 (56) = 0.10 (7.4833) + 1.68 = 0.74833 + 1.68 = 2.42833 dB/cm$ . Loss: $A_{56} = 24.28 dB$ . Why this step? Same trace, higher frequency — now we see which term dominates.
Ratio: $A_{56} / A_{28} = 24.28/13.69 \approx 1.774$ . Why this step? Doubling $f$ multiplied loss by ~1.77 — more than the $2 \approx 1.41$ you'd get from skin effect alone, because the dielectric term grows linearly and takes over at high $f$ . That over-1.5 growth is why copper "breaks" and CPO becomes necessary.

Verify: at high $f$ the $b f$ term dominates ( $1.68$ vs $0.748$ at 56 GHz) ✓; ratio $\approx 1.77 > 2$ ✓. Limiting behaviour: as $f \to \infty$ , $α \sim b f$ grows linearly, so loss is unbounded — no equalizer wins forever. Optics is the escape.

Cell G — the real-world word problem

Worked example Ex 7 (Cell G): a data-center's yearly electricity bill

A hyperscaler runs $N = 4000$ switches, each $51.2 Tb/s$ . Moving from faceplate ( $256 W$ I/O each) to CPO ( $51.2 W$ each) saves I/O power. If electricity costs $ $0.12$ per kWh, and switches run $24/7$ all year, how much money is saved per year? (Ignore cooling multiplier for now.)

Forecast: thousands of dollars? Hundreds of thousands? Millions?

Per-switch power saving: $256 - 51.2 = 204.8 W$ (from Ex 2). Why this step? We already computed this; reuse it — good engineers don't recompute.
Fleet saving: $204.8 W \times 4000 = 819, 200 W = 819.2 kW$ . Why this step? Power scales linearly with switch count; convert to kW because the tariff is per kWh.
Energy per year: hours in a year $= 24 \times 365 = 8760 h$ , so $819.2 kW \times 8760 h = 7, 176, 192 kWh$ . Why this step? Power (kW) × time (h) = energy (kWh) — the tariff's currency.
Cost saving: $7{,}176{,}192 \times \$ 0.12 = $861{,}143.04$ per year. Why this step? Energy × price = money. This is the CFO-facing number that funds CPO programs.

Verify: units: $\text{kW}\cdot\text{h}\cdot\tfrac{\$ }{\text{kWh}} = $ $✓. Order-of-magnitude: ~0.8 MW saved × ~\$ 1000/kW-year ≈ ~$0.86 M ✓. And this ignores cooling — real savings roughly double once you count the ~2× datacenter PUE overhead.

Cell H — the exam twist (solve backwards)

Worked example Ex 8 (Cell H): hit a power budget by choosing

$E_{b}$ An architect has a hard cap of $P_{max} = 40 W$ for the I/O of a next-gen $B = 102.4 Tb/s$ switch. What is the maximum allowable $E_{b}$ ?

Forecast: will the target be above or below today's $\sim 1 pJ/bit$ CPO number?

Rearrange the power law for the unknown $E_{b}$ : $P = E_{b} B \Rightarrow E_{b} = \frac{P}{B}$ Why this step? The question inverts the usual direction — we know $P$ and $B$ , want $E_{b}$ . Algebra simply divides both sides by $B$ .
Plug in: $E_{b} = \frac{40 W}{102.4 \times 1 0 ^{12} bit/s} = 3.906 \times 1 0^{- 13} J/bit = 0.39 pJ/bit$ Why this step? Keep base SI units so the answer lands in J/bit, then convert to the readable pJ/bit ( $\times 1 0^{12}$ ).

Verify: $E_{b} \times B = 0.39 \times 1 0^{- 12} \times 102.4 \times 1 0^{12} = 0.39 \times 102.4 \approx 40 W$ ✓. Interpretation: $0.39 pJ/bit$ is below today's ~1 pJ/bit — proving the target is aggressive, exactly why the roadmap in the parent note pushes toward ~1 pJ/bit and beyond. Prerequisite context: SerDes and Wireline Links and Switch ASIC Bandwidth Scaling.

Recall Quick self-test on the matrix

Which cell does "power still isn't zero at $L = 0$ " belong to? ::: Cell D — the degenerate/limit case, answer $\approx 40.96 W$ . Why is the whole-link saving ~50% while the SerDes slice is 80%? ::: Same absolute watts saved, but divided by a larger base that includes the fixed optical floor (Cell C). As lane rate doubles $28 \to 56 GHz$ , loss grows by a factor of about? ::: ~1.77 — more than $2$ because the dielectric $b f$ term takes over (Cell F).

Related vault topics: Silicon Photonics · Linear Pluggable Optics (LPO) · Pluggable Optical Modules (QSFP-DD, OSFP) · 2.5D and 3D Packaging · Thermal Management in Packages · Data Center Network Topologies