Co-packaged optics trends: Worked examples — Hinglish deep dive

6.5.18 · D3 · Hardware › Advanced & Emerging Architectures › Co-packaged optics trends

Pehle kuch bhi shuru karne se, aao in dono symbols ko dobara earn karte hain taaki koi naya padhne wala kabhi na uljhe:

Scenario matrix

Is topic ke har case inn cells mein se kisi ek mein aata hai. Neeche ke examples mein cell label laga hua hai, aur milke yeh har row fill karte hain.

Cell	Kya stress karta hai	Degenerate/limit?	Example
A. Baseline compute	$P = E_{b} B$ mein numbers plug karo	nahi	Ex 1
B. Savings / ratio	Do $E_{b}$ values compare karo	nahi	Ex 2
C. Scope trap	80% vs 30–50% — sahi number sahi scope ke liye	nahi	Ex 3
D. Zero / degenerate	$L \to 0$ , $E_{b} \to$ floor	haan	Ex 4
E. Loss law + length	$A = α (f) L$ , reach aadhi karo	$L$ mein limiting	Ex 5
F. Frequency scaling	$α (f) = a f + b f$ , lane rate badhao	$f$ mein limiting	Ex 6
G. Real-world word problem	rack of switches, electricity bill	nahi	Ex 7
H. Exam twist	ulta solve karo $E_{b}$ target ke liye	inverse	Ex 8

Cell A — baseline computation

Worked example Ex 1 (Cell A): 51.2 Tb/s switch ka interface power

Ek switch ASIC $B = 51.2 Tb/s$ move karta hai long-reach faceplate SerDes par $E_{b} = 5 pJ/bit$ ke saath. Electrical-interface power kya hai?

Forecast: guess karo — kya yeh tens of watts hai, hundreds, ya thousands? Apna guess likho.

Dono numbers ko base SI units mein convert karo. $E_{b} = 5 pJ/bit = 5 \times 1 0^{- 12} J/bit$ , aur $B = 51.2 Tb/s = 51.2 \times 1 0^{12} bit/s$ . Yeh step kyun? Formula tabhi watts dega jab hum joules aur bits/s feed karein. pJ ko Tb/s ke saath mix karna cancellation "chhupa" deta hai aur off-by- $1 0^{24}$ blunder invite karta hai.
Multiply karo. $P = (5 \times 1 0^{- 12}) \times (51.2 \times 1 0^{12}) = 5 \times 51.2 = 256 W$ Yeh step kyun? $1 0^{- 12}$ aur $1 0^{+ 12}$ exactly cancel ho jaate hain — yahi wajah hai ki pJ/bit aur Tb/s natural units hain yahan: exponents ek doosre ko khatam karne ke liye engineer kiye gaye hain.

Verify: units $= \frac{J}{bit} \cdot \frac{bit}{s} = W$ . ✓ Sanity: 256 W roughly do bright desktop-PC power supplies ke barabar hai — ek poore rack-top switch ke sirf I/O ke liye plausible hai, aur exactly yahi wajah hai ki engineers panic karte hain.

Cell B — savings ratio

Worked example Ex 2 (Cell B): CPO yahan kitna bachata hai?

Wahi switch. CPO electrical reach ko millimetres tak shrink kar deta hai, jisse $E_{b}$ $5$ se gir ke $1 pJ/bit$ ho jaata hai. Naya power aur fractional saving nikalo.

Forecast: ratio $5 \to 1$ — power ka kaunsa fraction gayab ho jaata hai?

Naye $E_{b}$ ke saath recompute karo. $P_{CPO} = (1 \times 1 0^{- 12}) (51.2 \times 1 0^{12}) = 51.2 W$ Yeh step kyun? $B$ unchanged hai (same switch throughput), isliye sirf $E_{b}$ move hota hai — ek clean controlled comparison.
Fractional saving lo: $saving = \frac{P _{old} - P _{new}}{P _{old}} = \frac{256 - 51.2}{256} = \frac{204.8}{256} = 0.8 = 80%$ Yeh step kyun? Ek ratio units hata deta hai aur improvement switch size se independent bata deta hai — kyunki $B$ cancel ho jaata hai, 80% cut kisi bhi $B$ ke liye hold karta hai jab tak $E_{b}$ $5 \to 1$ jaata hai.

Verify: $51.2 = 256/5$ , aur $5 \to 1$ exactly factor of 5 hai, isliye $1/5 = 20%$ bachta hai, $80%$ gaya. ✓ Ratio dimensionless hai ✓.

Cell C — scope trap (woh number jo logon ko fool karta hai)

Worked example Ex 3 (Cell C): headline 30–50% kyun hai, 80% kyun nahi

Parent note warn karta hai ki 80% figure sirf SerDes-reach slice ke liye hai. Maano poora link $256 W$ SerDes-reach power plus ek fixed $F = 120 W$ modulators, TIAs, DSP-lite aur laser inefficiency mein jalata hai jo CPO nahi hatata. Realistic whole-link saving kya hai?

Forecast: kya yeh abhi bhi 80% ke paas hoga, ya kam?

Old whole-link power: $P_{old} = 256 + 120 = 376 W$ . Yeh step kyun? "Whole-link" ek wider scope hai "SerDes-reach" se. Hume fixed floor $F$ add karna hoga jo dono technologies pay karti hain.
New whole-link power: SerDes slice $256 \to 51.2$ drop hota hai, floor ruka rehta hai. $P_{new} = 51.2 + 120 = 171.2 W$ . Yeh step kyun? CPO optical devices khud ko delete nahi kar sakta — pJ/bit floor zero nahi hai, exactly jaise parent note stress karta hai.
Fractional saving: $\frac{376 - 171.2}{376} = \frac{204.8}{376} \approx 0.545 = 54.5%$ Yeh step kyun? Same absolute watts saved ( $204.8 W$ ) lekin ek bade base se divide kiya → chhota percentage. Exactly yahi wajah hai ki scope headline badal deta hai.

Verify: absolute saving $204.8 W$ Ex 2 jaisa hi hai ✓; $54.5% < 80%$ ✓ aur yeh "30–50%-ish realistic" band mein aata hai jab aur floor add karo. Lesson: 80% sirf SerDes portion ke liye quote karo.

Cell D — zero / degenerate edge

Worked example Ex 4 (Cell D): jab reach

$\to 0$ ho toh kya hota hai? Monolithic optical I/O electrical reach $L \to 0$ push kar deta hai. Kya interface power bhi zero ho jaati hai? $E_{b} (L) = E_{floor} + k L$ use karo fixed floor $E_{floor} = 0.8 pJ/bit$ , slope $k = 0.14 pJ/bit per cm$ , usi $51.2 Tb/s$ switch par.

Forecast: kya power 0 W tak girti hai, ya kisi non-zero limit tak?

$L = 30 cm$ (faceplate) par model: $E_{b} = 0.8 + 0.14 (30) = 0.8 + 4.2 = 5.0 pJ/bit$ . Yeh step kyun? Hum model tune karte hain taaki faceplate case known $5 pJ/bit$ reproduce kare — extrapolate karne se pehle sanity-anchoring.
Limit $L \to 0$ lo: $lim_{L \to 0} E_{b} (L) = E_{floor} = 0.8 pJ/bit$ Yeh step kyun? Jaise length vanish hoti hai $k L$ term marta hai, lekin floor bachta rehta hai — driver, modulator aur receiver abhi bhi energy cost karte hain chahe wire ki length zero ho.
Toh limiting power hai: $P_{min} = (0.8 \times 1 0^{- 12}) (51.2 \times 1 0^{12}) = 40.96 W$ Yeh step kyun? Yeh hard floor hai: koi bhi packaging trick isse beat nahi kar sakti bina optical devices khud badle.

Verify: $L = 0$ par, $E_{b} = 0.8$ ; $0.8 \times 51.2 = 40.96 W$ , jo zero nahi hai ✓. Degenerate case ek key truth sikhata hai: length shrink karna ek non-zero floor ki taraf diminishing returns deta hai, kabhi zero ki taraf nahi.

Cell E — loss law aur length

Worked example Ex 5 (Cell E): copper budget, faceplate vs CPO

Ek copper channel ek lane rate par attenuation coefficient $α = 1.6 dB/cm$ rakhta hai (yeh frequency pehle se bake in hai). Faceplate reach $L_{1} = 25 cm$ versus CPO reach $L_{2} = 0.5 cm$ ke liye equalizer ko recover karne wala loss compare karo.

Forecast: dB budget roughly kitne factor se shrink hoga?

Faceplate loss: $A_{1} = α L_{1} = 1.6 \times 25 = 40 dB$ . Yeh step kyun? $A = α L$ length mein linear hai, isliye hum sirf multiply karte hain — geometry origin se ek seedhi line hai (figure dekho).
CPO loss: $A_{2} = α L_{2} = 1.6 \times 0.5 = 0.8 dB$ . Yeh step kyun? Same coefficient, tiny length — CPO ka poora point yahi hai ki us seedhi line par left slide karo.
Ratio of budgets: $A_{1} / A_{2} = 40/0.8 = 50$ . Yeh step kyun? Kyunki loss $L$ mein linear hai, loss ratio length ratio $25/0.5 = 50$ ke barabar hai. Linearity hi "wire chhotaa karo" ko direct dB win banata hai.

Verify: $L_{1} / L_{2} = 25/0.5 = 50 = A_{1} / A_{2}$ ✓. 40 dB budget matlab received signal power mein $1 0^{4}$ × kamzor — brutal DSP; 0.8 dB almost free hai. Figure par red dot origin ke paas baitha hai: woh CPO hai.

Cell F — frequency scaling ( $f$ mein limiting behaviour)

Worked example Ex 6 (Cell F): 224 Gb/s "copper ko kyun tod deta hai"

Loss per cm hai $α (f) = a f + b f$ jahan $a = 0.10 \frac{dB}{cm GHz}$ (skin effect) aur $b = 0.03 \frac{dB}{cm GHz}$ (dielectric). PAM4 lane ki key frequency roughly (line-rate/4) GHz mein hoti hai. $112 Gb/s$ (Nyquist $\approx 28 GHz$ ) ko $224 Gb/s$ (Nyquist $\approx 56 GHz$ ) se compare karo ek $10 cm$ trace par.

Forecast: kya rate double karne se loss roughly double hoga, ya zyada?

$f = 28 GHz$ par: $α = 0.10 28 + 0.03 (28) = 0.10 (5.2915) + 0.84 = 0.52915 + 0.84 = 1.36915 dB/cm$ . Loss over $10 cm$ : $A_{28} = 13.69 dB$ . Yeh step kyun? Hum skin effect ke liye $f$ use karte hain (current wire ki surface par crowd karta hai, frequency ke saath bura hota hai) aur dielectric ke liye linear $f$ (insulator zyada energy absorb karta hai jab woh tezee se wiggle karta hai) — do alag physics, isliye do terms.
$f = 56 GHz$ par: $α = 0.10 56 + 0.03 (56) = 0.10 (7.4833) + 1.68 = 0.74833 + 1.68 = 2.42833 dB/cm$ . Loss: $A_{56} = 24.28 dB$ . Yeh step kyun? Same trace, higher frequency — ab hum dekhte hain kaunsa term dominate karta hai.
Ratio: $A_{56} / A_{28} = 24.28/13.69 \approx 1.774$ . Yeh step kyun? $f$ double karne se loss ~1.77 guna hua — $2 \approx 1.41$ se zyada jo sirf skin effect se milta, kyunki dielectric term linearly grow karta hai aur high $f$ par overtake le leta hai. Yahi over-1.5 growth hai jo copper ko "tod" deta hai aur CPO ko zaroori banata hai.

Verify: high $f$ par $b f$ term dominate karta hai ( $1.68$ vs $0.748$ at 56 GHz) ✓; ratio $\approx 1.77 > 2$ ✓. Limiting behaviour: jaise $f \to \infty$ , $α \sim b f$ linearly grow karta hai, isliye loss unbounded hai — koi bhi equalizer forever nahi jeetta. Optics escape hai.

Cell G — real-world word problem

Worked example Ex 7 (Cell G): data-center ka yearly electricity bill

Ek hyperscaler $N = 4000$ switches chalata hai, har ek $51.2 Tb/s$ . Faceplate ( $256 W$ I/O each) se CPO ( $51.2 W$ each) mein move karne se I/O power bachti hai. Agar electricity $ $0.12$ per kWh cost karti hai, aur switches $24/7$ poore saal chalte hain, toh per year kitna paisa bachta hai? (Abhi cooling multiplier ignore karo.)

Forecast: thousands of dollars? Hundreds of thousands? Millions?

Per-switch power saving: $256 - 51.2 = 204.8 W$ (Ex 2 se). Yeh step kyun? Yeh hum pehle compute kar chuke hain; reuse karo — acche engineers recompute nahi karte.
Fleet saving: $204.8 W \times 4000 = 819, 200 W = 819.2 kW$ . Yeh step kyun? Power switch count ke saath linearly scale hota hai; kW mein convert karo kyunki tariff per kWh hai.
Energy per year: saal mein ghante $= 24 \times 365 = 8760 h$ , toh $819.2 kW \times 8760 h = 7, 176, 192 kWh$ . Yeh step kyun? Power (kW) × time (h) = energy (kWh) — tariff ki currency.
Cost saving: $7{,}176{,}192 \times \$ 0.12 = $861{,}143.04$ per year. Yeh step kyun? Energy × price = money. Yeh CFO-facing number hai jo CPO programs ko fund karta hai.

Verify: units: $\text{kW}\cdot\text{h}\cdot\tfrac{\$ }{\text{kWh}} = $ $✓. Order-of-magnitude: ~0.8 MW saved × ~\$ 1000/kW-year ≈ ~$0.86 M ✓. Aur yeh cooling ignore karta hai — real savings roughly double ho jaati hain jab ~2× datacenter PUE overhead count karo.

Cell H — exam twist (ulta solve karo)

Worked example Ex 8 (Cell H): power budget hit karo

$E_{b}$ choose karke Ek architect ke paas next-gen $B = 102.4 Tb/s$ switch ke I/O ke liye hard cap $P_{max} = 40 W$ hai. Maximum allowable $E_{b}$ kya hai?

Forecast: kya target aaj ke ~1 pJ/bit CPO number se upar hoga ya neeche?

Power law ko unknown $E_{b}$ ke liye rearrange karo: $P = E_{b} B \Rightarrow E_{b} = \frac{P}{B}$ Yeh step kyun? Question usual direction invert karta hai — hume $P$ aur $B$ pata hai, $E_{b}$ chahiye. Algebra sirf dono sides ko $B$ se divide karta hai.
Plug in karo: $E_{b} = \frac{40 W}{102.4 \times 1 0 ^{12} bit/s} = 3.906 \times 1 0^{- 13} J/bit = 0.39 pJ/bit$ Yeh step kyun? Base SI units rakho taaki answer J/bit mein aaye, phir readable pJ/bit mein convert karo ( $\times 1 0^{12}$ ).

Verify: $E_{b} \times B = 0.39 \times 1 0^{- 12} \times 102.4 \times 1 0^{12} = 0.39 \times 102.4 \approx 40 W$ ✓. Interpretation: $0.39 pJ/bit$ aaj ke ~1 pJ/bit se neeche hai — yeh prove karta hai ki target aggressive hai, exactly yahi wajah hai ki parent note ka roadmap ~1 pJ/bit aur usse aage push karta hai. Prerequisite context: SerDes and Wireline Links aur Switch ASIC Bandwidth Scaling.

Recall Matrix par quick self-test

" $L = 0$ par power abhi bhi zero nahi hai" — yeh kaunse cell mein aata hai? ::: Cell D — degenerate/limit case, answer $\approx 40.96 W$ . Whole-link saving ~50% kyun hai jabki SerDes slice 80% hai? ::: Same absolute watts saved, lekin ek bade base se divide kiya jisme fixed optical floor bhi hai (Cell C). Jab lane rate $28 \to 56 GHz$ double hoti hai, loss roughly kitne factor se badhti hai? ::: ~1.77 — $2$ se zyada kyunki dielectric $b f$ term over le leta hai (Cell F).

Related vault topics: Silicon Photonics · Linear Pluggable Optics (LPO) · Pluggable Optical Modules (QSFP-DD, OSFP) · 2.5D and 3D Packaging · Thermal Management in Packages · Data Center Network Topologies