Co-packaged optics trends — Hinglish notes

6.5.18 · Hardware › Advanced & Emerging Architectures

Co-packaged Optics HAI KYA?

Integration ka spectrum:

Stage	Optics location	Electrical reach needed	Trend
Pluggable	Faceplate	~10–30 cm	Legacy
On-board optics (OBO)	PCB par ASIC ke paas	~5–10 cm	Interim
Co-packaged optics	ASIC package par	~1–5 mm	Emerging
Monolithic/optical I/O	Die ke andar / chiplet	~0	Future

KYUN chahiye? (First principles se pressure derive karo)

Poori motivation yeh hai ki energy aur signal loss, switch bandwidth se faster scale karte hain.

Chaliye numbers lagate hain.

Worked example Ek 51.2 Tb/s switch ke liye faceplate power

Maano long-reach faceplate SerDes $E_{b} \approx 5 pJ/bit$ par hai. $P = 5 \times 1 0^{- 12} \frac{J}{bit} \times 51.2 \times 1 0^{12} \frac{bit}{s} = 256 W$ Yeh step kyun? Energy/bit ko bits/s se multiply karo → joules/s = watts. Yeh ~256 W sirf electrical I/O ke liye hai, switch core ke upar se. Isliye SerDes ka "tax" unsustainable hai.

Ab CPO ke saath, die-to-optics reach millimeters hai, toh $E_{b}$ ~ $1 pJ/bit$ tak drop ho sakta hai: $P = 1 \times 1 0^{- 12} \times 51.2 \times 1 0^{12} = 51.2 W$ Bachhat ≈ 200 W per switch — is idealized $5 \to 1$ pJ/bit comparison mein yeh I/O link power mein ~~80% ki katauti** hai. Real deployments mein poore-link ki saving thodi kam hoti hai (~~30–50%**), kyunki CPO mein abhi bhi drivers, TIAs, DSP-lite aur optical devices khud hain — pJ/bit floor zero nahi hai. ~30–50% link-power reduction ko realistic headline ke roop mein quote karo; 80% figure sirf is specific example mein SerDes-reach portion par laagu hoti hai.

CPO BANTA KAISE HAI?

Key enabling technologies (woh 80/20 jo aapko pata hona chahiye):

Silicon photonics — CMOS-compatible processes mein waveguides/modulators/detectors build karo → sasta, integrable, wafer-scale.
2.5D packaging — optical engine + ASIC ek shared interposer/organic substrate par fine-pitch bumps ke saath.
Advanced fiber attach — precise coupling (grating couplers / edge couplers) jo thermal cycling survive kare.
Thermal management — optics ko heat se nafrat hai; ring resonators drift karte hain, lasers redshift hoti hain. Ek hot ASIC ke saath co-locate karna central engineering headache hai.

Trade-offs (objections ko steel-man karo)

Trends timeline (yaad rakhne wale numbers)

Bandwidth doubling ~har 2 saal mein: 12.8 → 25.6 → 51.2 → 102.4 Tb/s switch ASICs.
Per-lane electrical SerDes: 112 Gb/s (PAM4) → 224 Gb/s — jahaan copper reach sach mein toot jaati hai.
Target CPO metric: < 5 pJ/bit end-to-end, ~1 pJ/bit optical I/O ki taraf.
Standards/consortia: OIF, CPO Collaboration, hyperscaler demos (e.g., 51.2 Tb/s CPO switches).

Recall Feynman: 12-saal ke bachche ko explain karo

Socho tumhara computer chip apne messages friends ko ek bade kamre ke paar shout karke bhejta hai. Jitna door shout, utni zyada energy chahiye aur words bhi bigad jaate hain. Abhi "friends" (woh parts jo messages ko fiber cables ke liye light mein convert karte hain) door darwaaze par baitha hai. Co-packaged optics un friends ko chip ke bilkul paas le aata hai, toh poore kamre mein shout karne ki jagah, chip sirf ek centimeter mein whisper karta hai — wahi message, bahut kam energy, aur zyada saaf aata hai. Catch yeh hai: woh friends ab chip ke bilkul saath jude hain, toh agar ek toot jaaye toh usse aasaani se swap nahi kar sakte.

Flashcards

Co-packaged optics kya hai?

Optical transceiver ko switch/compute ASIC ke same package/substrate par rakhna, ASIC-to-optics electrical reach ko ~cm se ~mm tak shrink karna.

CPO ki primary motivation kya hai?

Electrical SerDes power aur channel loss switch bandwidth ke saath super-linearly scale karte hain; electrical reach shortening se energy/bit cut hoti hai.

Electrical interface power ka formula?

P = E_{b} \times B

(energy per bit × aggregate bandwidth).

51.2 Tb/s par 5 pJ/bit interface power kya hogi?

5 pJ \times 51.2 Tb/s = 256

Shorter electrical reach energy/bit kyun kam karta hai?

Copper loss ∝ length (aur ∝ ~√f + f); short reach mein bahut kam equalization/DSP chahiye, toh ek tiny low-power SerDes kaafi hai.

Laser often external (ELS) kyun rakhi jaati hai?

Lasers sabse kam reliable, sabse zyada temperature-sensitive component hain; unhe serviceable/hot package se bahar rakhna reliability improve karta hai.

CPO vs monolithic optics mein kya fark hai?

CPO = same package par alag chiplets; monolithic = optics khud logic die mein build ki gayi.

Pluggables ke comparison mein CPO ka sabse bada downside?

Field serviceability aur modularity ka loss — ek dead engine matlab switch scrap karna pad sakta hai.

LPO/LRO kya hain aur kyun exist karte hain?

Linear Pluggable/Receive Optics DSP retimer hata dete hain lekin pluggable form factor rakhte hain — zyaatar power win, kam serviceability risk ke saath.

CPO ke liye key enabling tech kya hai?

Silicon photonics + 2.5D/interposer packaging + precise fiber attach + thermal management.

CPO ki central engineering headache kya hai?

Thermal — optics (rings, lasers) temperature ke saath drift karte hain lekin ek bahut hot ASIC ke paas baithna padta hai.

CPO se realistic whole-link power saving kitni hai?

Link power ka roughly 30–50% (~80% figure sirf idealized SerDes-reach portion par laagu hoti hai, 5→1 pJ/bit example mein).

Connections

Silicon Photonics
SerDes and Wireline Links
2.5D and 3D Packaging
Pluggable Optical Modules (QSFP-DD, OSFP)
Linear Pluggable Optics (LPO)
Switch ASIC Bandwidth Scaling
Thermal Management in Packages
Data Center Network Topologies