Advanced & Emerging Architectures

Q1. (5 marks)

• Chiplet definition: A small, functionally-complete integrated-circuit die designed to be combined with other dies inside a single package to form a larger system. (2)
• Advantages (any two, 1.5 each):
  • Improved yield — smaller dies have fewer defects each, raising manufacturing yield vs. one large die. (1.5)
  • Heterogeneous integration / mix-and-match process nodes — e.g. compute on advanced node, I/O on cheaper mature node. (1.5)
  • (Also accept: modularity/reuse, lower cost, faster time-to-market.) Why: Defect probability scales with die area, so partitioning improves yield; different functions have different optimal nodes.

Q2. (6 marks)

• 2.5D: Multiple dies placed side-by-side on a shared silicon interposer which routes dense interconnect between them; dies are not stacked vertically. (2)
• 3D stacking: Dies stacked vertically on top of one another, connected through the silicon body. (2)
• Interposer: A passive silicon (or organic) layer providing fine-pitch wiring between chiplets. (1)
• TSV: A vertical electrical connection passing through the silicon substrate, enabling die-to-die signalling in 3D stacks (and interposers). (1)

Q3. (5 marks) (a) Bandwidth $= \dfrac{\text{width} \times \text{data rate}}{8}$ $= \frac{1024 \text{ bits} \times 2.0\times10^{9}\text{ /s}}{8} = 256\times10^{9}\text{ B/s} = 256 \text{ GB/s}$ Working (2), correct answer 256 GB/s (1). (b) HBM uses a very wide interface (1024-bit) via a short interposer/TSV connection, allowing many parallel bits at moderate clock, whereas GDDR6 uses a narrower bus at higher clock on the PCB. (2)

Q4. (4 marks)

• PIM idea: Move computation into or near the memory arrays so data is processed where it is stored, rather than transferring it to a distant CPU/GPU. (2)
• Problem reduced: The memory wall / von Neumann data-movement bottleneck — the energy and latency cost of moving data between memory and processor. (2)

Q5. (5 marks) (a) A systolic array is a grid of tightly-coupled PEs through which data is rhythmically pumped, each PE computing and passing partial results to neighbours. (2) (b) Multiplying two $256\times256$ matrices requires $N^3 = 256^3 = 16\,777\,216 \text{ MACs.}$ Formula $N^3$ (1), substitution (1), answer $16{,}777{,}216$ (1).

Q6. (4 marks)

• NPU definition: A domain-specific accelerator optimised for neural-network operations (matrix/tensor multiply, convolution, activation). (2)
• Efficiency reason (any one): Specialised MAC datapaths + on-chip data reuse reduce instruction-fetch/decode overhead and off-chip memory traffic; often uses reduced-precision (INT8) arithmetic which is cheaper per operation. (2)

Q7. (4 marks)

• Control-flow (von Neumann): Execution order is driven by a program counter; an instruction runs when the PC reaches it. (2)
• Dataflow: An instruction/operation fires as soon as all its input operands (data) are available, exposing parallelism naturally with no central PC. (2)

Q8. (4 marks) (a) Field-Programmable Gate Array. (1) (b) Advantages (any two, 1 each): reconfigurable/reprogrammable after manufacture; lower NRE cost and faster time-to-market; good for low/medium volume. (2) Disadvantage (1): lower clock speed / higher power / lower area-efficiency than an equivalent ASIC. (1)

Q9. (5 marks) (a) A qubit is a quantum two-level system whose state can be a superposition $\alpha|0\rangle + \beta|1\rangle$. (2) An $n$-qubit register can represent $2^n$ basis states simultaneously. (1) (b) $2^{10} = 1024$ basis states. (2)

Q10. (5 marks, 1 each) (a) Neuromorphic: Hardware that mimics biological neurons/synapses, typically using spiking, event-driven computation. (b) Photonic interconnect: Data communication using light (photons) in optical waveguides/fibres instead of electrical wires. (c) Approximate computing: Trading small, tolerable losses in result accuracy for gains in speed, energy, or area. (d) Wafer-scale engine: A single processor built from an entire silicon wafer rather than being diced into separate chips. (e) Co-packaged optics: Integrating optical transceivers into the same package as the switch/processor die to shorten electrical paths and cut interconnect energy.

[
  {"claim":"HBM2 bandwidth = 256 GB/s for 1024-bit @ 2.0 Gbit/s/pin","code":"width=1024; rate=2.0e9; bw=width*rate/8; result = (bw == 256e9)"},
  {"claim":"256x256 matmul needs 256**3 MACs = 16777216","code":"result = (256**3 == 16777216)"},
  {"claim":"10-qubit register spans 2**10 = 1024 states","code":"result = (2**10 == 1024)"}
]