Hum do cheezein care karte hain: energy per bit aur achievable bandwidth.
Step 1 — Wire ko ek capacitor ki tarah model karo.
Kyun? Signal bhejne ka matlab hai wire ki capacitance C ko charge/discharge karna. L length ki wire mein:
C=c⋅L
jahan c capacitance per unit length hai (F/m). Yeh step kyun? Capacitance usse badhti hai jitna conductor hota hai, yaani length ke saath.
Step 2 — Ek bit bhejna ka energy.
Capacitor C ko voltage V tak charge karne ki energy:
Ebit=21CV2=21cLV2Kyun? Standard capacitor charging energy 21CV2. Toh energy linearly lengthL ke saath scale karti hai.
Step 3 — Interposer vs PCB compare karo.
Silicon interposer wires ~100× chhoti hoti hain (µm nahi mm) aur fine geometry c ko kam karta hai. Toh:
EPCBEinterposer∼LPCBLint≪1
Roughly order of magnitude kam energy per bit.
Step 4 — Parallelism se bandwidth.
Total bandwidth hai:
BW=Nwires×fsignal
Kyunki interposer wires ~1 µm pitch par pack ho sakti hain vs PCB par ~100 µm, Nwires ~1002 jump karta hai agar aap 2D area count karein, ya ~100× per edge length. Isliye HBM (High Bandwidth Memory) ko interposer chahiye — yeh 1024-bit-wide bus use karta hai jo koi PCB route nahi kar sakta.
Yeh chiplets ke neeche ek passive silicon substrate hai jo ultra-dense, short wiring (aur TSVs) carry karta hai taaki chiplets high bandwidth aur low energy par connect ho sakein.
2.5D aur 3D packaging mein kya fark hai?
2.5D = chiplets interposer par side-by-side (horizontal). 3D = active dies ek doosre ke upar vertically stack hote hain.
Chhote chiplets yield kyun improve karte hain?
Yield Y=e−DA die area A ke saath girti hai; bade die ko chhote mein todne se har ek ki yield zyada hoti hai aur defects kam silicon waste karte hain.
Wire par energy per bit ka formula kya hai, aur uska kya matlab hai?
Ebit=21cLV2; energy wire length ke saath scale karti hai, isliye chhote interposer wires energy bachate hain.
TSV kya hai aur yeh kis direction mein jaata hai?
Through-Silicon Via — ek vertical copper via jo silicon thickness se pass hokar neeche layers/package se connect karta hai.
HBM ko interposer kyun chahiye?
Uska ~1024-bit-wide bus hazaaron fine-pitch wires maangta hai jo PCB (~100 µm pitch) route nahi kar sakta; sirf chip-grade interposer wiring (~1 µm) kar sakti hai.
Reticle limit kya hai aur yeh kyun matter karta hai?
Woh maximum area (~858 mm²) jo lithography exposure pattern kar sakta hai; aap monolithic die ko isse bada nahi bana sakte, isliye chiplet approach zaroori hoti hai.
Classic interposer active hai ya passive?
Passive — sirf wiring aur TSVs, transistors nahi (active interposers with logic newer exception hain).
Recall Feynman: ek 12-saal ke bachhe ko samjhaao
Socho ek bada LEGO castle ek giant piece se bana rahe ho — agar koi bhi tiny part toot gaya, toh poori cheez kharab ho jaati hai aur sab throw karna padta hai. Iske bajaye, ise chhote bricks se banao: agar ek brick kharab ho, sirf wahi toss karo. Ab tumhe bricks ko ek doosre se bahut tez baat karni hai, toh unhe ek special baseplate par rakhte ho jis par hazaaron tiny wires hain — door-door pieces ke beech lambi floppy cables se kahin better. Woh baseplate hai interposer, chhote bricks hain chiplets, aur unhe side-by-side rakhna hai 2.5D packaging.
