Worked examples — 2.5D packaging and interposers

This page is the drill floor for 2.5D packaging and interposers. The parent note gave you the tools; here we run them through every case they can be thrown at — big dies and tiny dies, defect densities of zero and infinity, energy comparisons, bandwidth budgets, a real-world word problem, and an exam-style trap.

Before the numbers, one promise: every symbol used below is defined by the parent note or re-defined here. If you see $Y$, $D$, $A$, $c$, $L$, $V$, $N$, $f$ for the first time, the table right under this line tells you what each means.

The two master formulas we reuse everywhere (from the parent):

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The scenario matrix

Every worked example below is tagged with the cell of this matrix it covers. Together they touch all of them.

Cell	What varies	The "edge" we test
C1 Small area	$A$ small	Yield near 1 — chiplet regime
C2 Large area	$A$ large	Yield collapses — monolithic regime
C3 Zero defects	$D=0$	Degenerate: $Y=1$, chiplets give no yield benefit
C4 Huge defects	$D\to \infty$	Limiting: $Y\to 0$, nothing survives
C5 Split-vs-whole	fixed total $A$, more cuts	How many chiplets is "enough"?
C6 Energy ratio	$L,c$ change	Interposer vs PCB energy per bit
C7 Bandwidth budget	$N,f$	Does the bus fit? (word problem)
C8 Exam twist	mixed	Overhead costs / when 2.5D loses

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C1 + C2 — Yield at both extremes

1. Plug small area. $Y_a=e^{-0.4\times 0.5}=e^{-0.2}$. Why this step? $Y=e^{-DA}$ is the probability of zero defects on the die; small $A$ ⇒ small exponent ⇒ $Y$ near 1.
2. Evaluate: $e^{-0.2}\approx 0.8187$ → ≈ 81.9% good.
3. Plug large area. $Y_b=e^{-0.4\times 8}=e^{-3.2}$. Why this step? Same formula; large $A$ ⇒ large exponent ⇒ $Y$ crushed toward 0.
4. Evaluate: $e^{-3.2}\approx 0.0408$ → ≈ 4.1% good.

Recall Why does area hurt so violently?

Because area sits in the exponent. Doubling area doesn't halve yield — it squares the survival penalty. This exponential is the entire economic reason chiplets exist.

Verify: exponents $-0.2$ and $-3.2$ have the right sign (negative → $Y<1$). The tiny die (81.9%) beats the giant (4.1%) by ~20×, matching the "small dies dodge defects" intuition.

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C3 + C4 — The degenerate limits

1. Zero-defect case. $Y=e^{-0\times A}=e^0=1$ for any $A$. Why this step? If no defects ever land, every die — big or small — is perfect. The exponent vanishes.
2. Consequence: when $D=0$, chiplets give zero yield advantage. The yield argument for 2.5D only exists because $D>0$. (2.5D can still win on reticle limit and node-mixing, but not on yield here.)
3. Huge-defect case. $Y=e^{-10\times 1}=e^{-10}\approx 4.54\times 10^{-5}$. Why this step? Large mean number of defects ⇒ near-certain that at least one lands ⇒ almost nothing survives.
4. Limit check: as $D\to \infty$, $e^{-DA}\to 0$. No packaging trick saves you from a broken fab.

Verify: $D=0\Rightarrow e^0=1$ (independent of $A$, correct degenerate behaviour). $e^{-10}\approx 4.5\times 10^{-5}$ is a tiny positive number — never exactly zero, so even a bad fab yields some silicon, as physics demands.

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C5 — How many chiplets is "enough"?

1. Per-chiplet area is $A_n=4/n$. Per-chiplet yield $y_n=e^{-0.5\cdot 4/n}=e^{-2/n}$. Why this step? Cutting the system into $n$ pieces shrinks each piece's area, raising each piece's individual survival probability.
2. Monolith $n=1$: $y_1=e^{-2}\approx 0.135$ → 13.5% of whole chips good.
3. 4 chiplets $n=4$: $y_4=e^{-0.5}\approx 0.607$ → each chiplet 60.7% good.
4. 16 chiplets $n=16$: $y_{16}=e^{-0.125}\approx 0.882$ → each chiplet 88.2% good. Why this step? As $n$ grows, the exponent $-2/n\to 0$, so $y_n\to 1$ — each tiny die becomes near-perfect.
5. The catch (why not infinite chiplets?): every extra cut adds microbumps, interposer wiring, and assembly cost. Yield of individual dies keeps climbing with diminishing return, while packaging overhead climbs linearly. That trade-off — not yield alone — sets the sweet spot (usually 2–8 chiplets in practice, see Chiplets and Heterogeneous Integration).

Recall What does

$e^{-2/n}$ approach as $n\to \infty$? ${\lim }_{n\to \infty }{e}^{-2/n}=e^0=1$. Individual yield saturates at 1 — pure diminishing returns.

Verify: the sequence $0.135,0.607,0.882$ is strictly increasing toward 1 as $n$ grows, and each equals $e^{-2/n}$. The gaps shrink ($0.607-0.135=0.472$ vs $0.882-0.607=0.275$) — confirming diminishing returns.

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C6 — Energy per bit: interposer vs PCB

1. Energy formula. $E_{bit}=\frac{1}{2}cL{V}^2$. Why this step? Sending a bit means charging the wire's capacitance to $V$; the charging energy of a capacitor is $\frac{1}{2}C{V}^2$ with $C=cL$.
2. Compute $V^2$ once. $V^2=0.8^2=0.64{\text{V}}^2$. Why this step? Both cases share the same voltage, so factor it out to avoid re-work.
3. PCB: $E_{PCB}=\frac{1}{2}(2\times 10^{-10})(0.020)(0.64)=1.28\times 10^{-12}\text{J}$ = 1.28 pJ/bit.
4. Interposer: $E_{int}=\frac{1}{2}(2\times 10^{-10})(0.0002)(0.64)=1.28\times 10^{-14}\text{J}$ = 0.0128 pJ/bit.
5. Ratio. $E_{int}/E_{PCB}=L_{int}/L_{PCB}=0.2/20=0.01$ → 100× less energy. Why this step? With $c$ and $V$ identical, energy is purely proportional to length, so the ratio is the length ratio. (In reality the interposer's finer geometry lowers $c$ too, making the win even larger.)

Verify: units — $\text{F/m}\times \text{m}\times {\text{V}}^2=\text{F}\cdot {\text{V}}^2=\text{J}$ ✓. Numbers: $1.28\text{ pJ}$ vs $0.0128\text{ pJ}$, ratio exactly $0.01$. ✓

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C7 — Bandwidth budget (real-world word problem)

1. Raw bandwidth in bits/s. $BW=N\times f=1024\times 3.2\times 10^9=3.2768\times 10^{12}\text{bits/s}$. Why this step? Bandwidth is lanes × per-lane rate; each of the 1024 wires carries $f$ transfers/s of 1 bit each.
2. Convert to bytes/s. Divide by 8: $3.2768\times 10^{12}/8=4.096\times 10^{11}\text{B/s}=$ 409.6 GB/s. Why this step? Storage/bandwidth targets are quoted in bytes (8 bits = 1 byte).
3. Meet target? $409.6\text{GB/s}\ge 300\text{GB/s}$ → yes, comfortably.
4. Can a PCB route 1024 wires? At PCB pitch ~100 µm, 1024 wires need ~$1024\times 100\mu \text{m}=102.4\text{mm}$ of edge just for data — impossible along a ~5 mm die edge. At interposer pitch ~1 µm, they need only ~1 mm of edge. Why this step? Bandwidth from parallelism is useless if you can't physically place the wires; this is exactly why HBM ships on an interposer. See High Bandwidth Memory (HBM).

Recall Why can't a PCB carry HBM's bus?

1024 wires at 100 µm pitch ⇒ ~102 mm of routing edge; the die edge is only a few mm. Only ~1 µm interposer pitch fits them.

Verify: $1024\times 3.2\times 10^9=3.2768\times 10^{12}$ bits/s; ÷8 = $4.096\times 10^{11}$ B/s = 409.6 GB/s ≥ 300 ✓. PCB edge needed $1024\times 100\mu \text{m}=0.1024\text{ m}=102.4\text{ mm}$ ✓.

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C8 — The exam twist: when does 2.5D lose?

1. Monolith yield. $Y_{mono}=e^{-0.2\times 1}=e^{-0.2}\approx 0.8187$. Why this step? Baseline good-fraction of the single die.
2. Cost per good monolith (in "area units") $=A/Y=1/0.8187\approx 1.2215$. Why this step? If only 81.9% survive, you must fabricate $1/0.819$ dies-worth of area to get one good one.
3. Chiplet yield. each chiplet $y=e^{-0.2\times 0.5}=e^{-0.1}\approx 0.9048$; a system needs both good: $Y_{sys}=y^2=e^{-0.2}\approx 0.8187$. Why this step? Two independent dies must both pass; multiply probabilities. Notice $y^2=e^{-0.1\cdot 2}=e^{-0.2}$ — identical total silicon-yield to the monolith, because total area is unchanged!
4. Chiplet cost including overhead. Good silicon per system $=1/0.8187\approx 1.2215$, then apply the 40% packaging tax: $1.2215\times 1.4\approx 1.710$. Why this step? The interposer and assembly are real costs the monolith doesn't pay.
5. Compare. Monolith 1.2215 vs chiplet 1.710 → the monolith is cheaper here. Why this trap works: at small area, the yield gain from splitting is tiny (both give $e^{-0.2}$), so the 40% overhead dominates. Chiplets only win when $A$ is large (C2) so the yield gain outweighs overhead.

Verify: monolith cost $1/e^{-0.2}=e^{0.2}\approx 1.2214$; chiplet total yield $e^{-0.1\cdot 2}=e^{-0.2}$ (equals monolith), cost $e^{0.2}\times 1.4\approx 1.710$; $1.710>1.221$ so monolith wins ✓.

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Recap: which cell taught what

Recall Fill the matrix

C1/C2 — yield near 1 vs collapsed, all from the exponent ::: Small $A$ ⇒ $Y\approx 0.82$; large $A$ ⇒ $Y\approx 0.04$. Area lives in the exponent. C3 — $D=0$ implication ::: $Y=1$ for any area; chiplets give zero yield benefit. C4 — $D\to \infty$ limit ::: $Y\to 0$; no packaging saves a broken fab. C6 — energy ratio equals ::: the length ratio (when $c,V$ match): 100× shorter wire ⇒ 100× less energy. C7 — why HBM needs an interposer ::: 1024 wires won't fit at PCB pitch; only ~1 µm interposer pitch routes them. C8 — when chiplets lose ::: When area is small, yield gain is tiny and packaging overhead dominates.

Related builds: Wafer Yield and Defect Density, Reticle Limit and Lithography, 3D Stacking and TSVs, Moore's Law and its Slowdown, Package Substrate and Ball Grid Array.