Question bank — 2.5D packaging and interposers

False. Only the passive interposer sits below; the active chiplets stay side-by-side (horizontal). Vertical stacking of active dies is 3D, not 2.5D.

False. A classic interposer is passive — just dense metal wiring plus TSVs, no transistors. (Newer "active interposers" add logic, but that is an exception, not the default.)

False. A TSV is a Through-Silicon Via: it runs vertically through the silicon thickness to reach the package bumps below. Horizontal chiplet-to-chiplet routing is done by the interposer's metal layers.

True. Yield $Y=e^{-DA}$ falls sharply with area $A$, so four small dies each have far higher yield than one die of $4A$, and each defect wastes only a quarter of the silicon.

False. It is fabricated like a chip (chip-grade lithography), which is exactly why it achieves ~1 µm wire pitch instead of the ~100 µm pitch of a PCB.

True. There are no transistors on a passive interposer at all; the fine pitch comes from using chip-fab lithography on the wiring, independent of any active devices.

True. $E_{bit}=\frac{1}{2}cL{V}^2$ scales linearly with length $L$ (with $V$ and $c$ fixed), so half the length is roughly half the energy.

False. It does the opposite — it dodges the reticle limit by keeping each chiplet small enough to print, then integrating many of them in one package.

False. HBM's bottleneck is width (a ~1024-bit bus), not clock speed. A PCB's ~100 µm pitch physically cannot fit that many wires in the tiny available edge, regardless of frequency.

True (to first order). $BW=N_{wires}\times f$; holding $f$ fixed and raising $N_{wires}$ raises $BW$ — this is precisely why interposers favour many slow-ish parallel wires over few fast ones.

Error: the interposer sits between chiplets and the package substrate — it adds a layer, it doesn't replace one. Savings come from yield and node-mixing, not from deleting the substrate.

Error: yield is $Y=e^{-DA}$, which is exponential, not linear. Doubling area squares the good-fraction ($e^{-2DA}=(e^{-DA}{)}^2$), so failure rises much faster than 2×.

Error: a microbump is a tiny solder joint (~40–50 µm pitch) between chiplet and interposer surface; a TSV is a copper via drilled through the silicon. Different structure, different direction, different job.

Error: the per-wire signalling isn't the main win — it's the number of short parallel wires. Density (many lanes) and shortness (low energy) are what the interposer buys, per $BW=Nf$ and $E_{bit}=\frac{1}{2}cL{V}^2$.

Error: it's the reverse. Chiplets let each function use its own best node — logic on the newest node, SRAM/IO/analog on a cheaper older node — which a monolithic die cannot do. See Chiplets and Heterogeneous Integration.

Error: yield $Y=e^{-DA}$ collapses for large $A$ and the reticle limit caps die size. Past a point, chiplets on an interposer are both cheaper and the only manufacturable option.

Error: even at equal length the interposer's fine geometry lowers capacitance per unit length $c$, so $E_{bit}=\frac{1}{2}cL{V}^2$ is smaller. In practice the interposer wire is also far shorter, compounding the win.

Because active dies remain in a 2D side-by-side layout; only the passive interposer borrows the z-axis for a hidden wiring floor. It's more than 2D but not full vertical stacking of logic — hence "two-and-a-half".

When a defect kills a small chiplet you throw away only that small area; on a big die one defect scraps everything. Combined with the exponential yield gain, usable good silicon per wafer rises sharply.

Its ~1024-bit bus needs thousands of fine-pitch signals in a ~5 mm edge — only chip-grade ~1 µm interposer routing fits them; a ~100 µm PCB pitch cannot. See High Bandwidth Memory (HBM).

Sending a bit means charging or discharging the wire, and charge storage is exactly what capacitance measures. That lets us use $E=\frac{1}{2}C{V}^2$ to see energy scales with length. This ties back to Interconnect RC Delay and Wire Scaling.

A pure wiring layer has no transistors to fail and needs no advanced logic node, so it is cheap and high-yield — it adds connectivity without adding the defect risk of active silicon.

Faster clocking raises per-wire dynamic energy and RC-limited signal integrity, while width scales bandwidth cheaply via parallelism. Interposers make many parallel lanes practical, so width is the easier lever.

As transistor scaling slows (Moore's Law and its Slowdown) and die sizes hit the reticle limit, integrating optimally-nodes chiplets in-package became the cheaper path to more capability.

$Y=e^{-D\cdot 0}=e^0=1$, i.e. 100%. An infinitesimally small die essentially never contains a defect — the limiting reason tiny chiplets are so yield-friendly.

$Y=e^0=1$ for any area — a defect-free process yields every die regardless of size, which is why the chiplet argument only bites when $D>0$.

Often not for yield alone — the packaging, interposer, and microbump overhead can outweigh a small yield gain. The win shifts toward node-mixing and reuse rather than defect avoidance.

Marginally. The interposer's advantage is dense, short, high-bandwidth links; for a few slow signals a cheaper substrate route may suffice, so the interposer isn't automatically justified.

Yes for wiring density, no for length. Even touching dies can't route thousands of cross-die signals through their edges without an interposer's fine metal layers, though the energy-per-length benefit shrinks.

Each split adds microbumps, interposer wiring, and inter-chiplet communication energy/latency. Past an optimum, this overhead outweighs the shrinking per-chiplet yield gain, so there is a sweet spot, not "smaller is always better".