Question bank — 2.5D packaging and interposers

False. Sirf passive interposer neeche hota hai; active chiplets side-by-side (horizontal) rehte hain. Active dies ki vertical stacking 3D hai, 2.5D nahi.

False. Ek classic interposer passive hota hai — bas dense metal wiring aur TSVs, koi transistors nahi. (Newer "active interposers" logic add karte hain, lekin woh ek exception hai, default nahi.)

False. TSV ek Through-Silicon Via hai: yeh silicon ki thickness ke through vertically run karta hai neeche package bumps tak pahunchne ke liye. Horizontal chiplet-to-chiplet routing interposer ki metal layers se hoti hai.

True. Yield $Y=e^{-DA}$ area $A$ ke saath sharply girti hai, toh chaar chote dies mein se har ek ki yield kaafi zyada hogi ek $4A$ ke die se, aur har defect sirf ek chauthai silicon waste karta hai.

False. Yeh ek chip ki tarah fabricate hota hai (chip-grade lithography), aur yahi reason hai ki yeh ~1 µm wire pitch achieve karta hai PCB ke ~100 µm pitch ki jagah.

True. Ek passive interposer par bilkul bhi transistors nahi hote; fine pitch chip-fab lithography ko wiring par use karne se aata hai, kisi bhi active device se independent.

True. $E_{bit}=\frac{1}{2}cL{V}^2$ length $L$ ke saath linearly scale karta hai ($V$ aur $c$ fixed hone par), toh aadhi length roughly aadhi energy hai.

False. Yeh ulta karta hai — yeh reticle limit ko dodge karta hai har chiplet ko itna chhota rakh ke ki print ho sake, phir unhe ek package mein integrate kar ke.

False. HBM ki bottleneck width hai (~1024-bit bus), clock speed nahi. PCB ka ~100 µm pitch physically itne saare wires fit nahi kar sakta tiny available edge mein, frequency chahe jo bhi ho.

True (first order tak). $BW=N_{wires}\times f$; $f$ fixed rakh ke $N_{wires}$ badhane se $BW$ badhti hai — yahi reason hai ki interposers kai slow-ish parallel wires ko few fast ones par prefer karte hain.

Error: interposer chiplets aur package substrate ke beech mein hota hai — yeh ek layer add karta hai, replace nahi karta. Savings yield aur node-mixing se aati hain, substrate delete karne se nahi.

Error: yield $Y=e^{-DA}$ hai, jo exponential hai, linear nahi. Area double karne se good-fraction square ho jaata hai ($e^{-2DA}=(e^{-DA}{)}^2$), toh failure 2× se kaafi zyada tezi se badhti hai.

Error: microbump ek tiny solder joint hai (~40–50 µm pitch) chiplet aur interposer surface ke beech; TSV ek copper via hai jo silicon ke through drill ki gayi hai. Alag structure, alag direction, alag kaam.

Error: per-wire signalling main win nahi hai — yeh short parallel wires ki sankhya hai. Density (kai lanes) aur shortness (low energy) woh cheez hai jo interposer deta hai, $BW=Nf$ aur $E_{bit}=\frac{1}{2}cL{V}^2$ ke hisaab se.

Error: yeh ulta hai. Chiplets har function ko apna best node use karne dete hain — logic newest node par, SRAM/IO/analog saste older node par — jo ek monolithic die nahi kar sakta. Dekho Chiplets and Heterogeneous Integration.

Error: yield $Y=e^{-DA}$ bade $A$ ke liye collapse ho jaati hai aur reticle limit die size cap kar deta hai. Ek point ke baad, interposer par chiplets dono saste bhi hain aur manufactureable ka ek maatra option bhi.

Error: equal length par bhi interposer ki fine geometry capacitance per unit length $c$ kam karti hai, toh $E_{bit}=\frac{1}{2}cL{V}^2$ chhota hota hai. Practice mein interposer wire bhi kaafi chhoti hoti hai, jo win ko aur compound karta hai.

Kyunki active dies ek 2D side-by-side layout mein rehte hain; sirf passive interposer ek hidden wiring floor ke liye z-axis borrow karta hai. Yeh 2D se zyada hai lekin logic ki full vertical stacking nahi — isliye "two-and-a-half".

Jab ek defect ek chhote chiplet ko kharab karta hai toh tum sirf woh chhota area phenkte ho; ek bade die par ek defect sab kuch waste kar deta hai. Exponential yield gain ke saath, per wafer usable good silicon sharply badhta hai.

Uski ~1024-bit bus ko ~5 mm edge mein hazaaron fine-pitch signals chahiye — sirf chip-grade ~1 µm interposer routing unhe fit kar sakti hai; ~100 µm PCB pitch nahi kar sakti. Dekho High Bandwidth Memory (HBM).

Ek bit bhejna wire ko charge ya discharge karna hai, aur charge storage exactly wahi hai jo capacitance measure karta hai. Iska matlab hai ki hum $E=\frac{1}{2}C{V}^2$ use kar sakte hain yeh dekhne ke liye ki energy length ke saath scale karti hai. Yeh Interconnect RC Delay and Wire Scaling se juda hai.

Ek pure wiring layer mein fail hone ke liye koi transistors nahi hote aur koi advanced logic node ki zaroorat nahi hoti, toh yeh sasta aur high-yield hota hai — yeh active silicon ka defect risk add kiye bina connectivity add karta hai.

Faster clocking per-wire dynamic energy aur RC-limited signal integrity badhata hai, jabki width bandwidth ko parallelism ke through saste mein scale karti hai. Interposers kai parallel lanes ko practical banate hain, toh width aasaan lever hai.

Jaise transistor scaling slow ho rahi hai (Moore's Law and its Slowdown) aur die sizes reticle limit tak pahunch rahi hain, optimally-noded chiplets ko in-package integrate karna zyada capability ka sasta raasta ban gaya.

$Y=e^{-D\cdot 0}=e^0=1$, yaani 100%. Ek infinitesimally small die practically kabhi koi defect contain nahi karta — yahi limiting reason hai ki tiny chiplets itne yield-friendly kyun hain.

Kisi bhi area ke liye $Y=e^0=1$ — ek defect-free process har die yield karta hai size ki parwah kiye bina, isliye chiplet argument tabhi bite karta hai jab $D>0$.

Aksar sirf yield ke liye nahi — packaging, interposer, aur microbump overhead ek chhote yield gain se zyada ho sakta hai. Win node-mixing aur reuse ki taraf shift ho jaati hai, defect avoidance ki jagah.

Marginally. Interposer ka advantage dense, short, high-bandwidth links hai; kuch slow signals ke liye ek sasta substrate route kaafi ho sakta hai, toh interposer automatically justify nahi hota.

Wiring density ke liye haan, length ke liye nahi. Touching dies bhi bina interposer ki fine metal layers ke apne edges ke through hazaaron cross-die signals route nahi kar sakti, haalaanki energy-per-length benefit shrink ho jaati hai.

Har split microbumps, interposer wiring, aur inter-chiplet communication energy/latency add karta hai. Ek optimum ke baad, yeh overhead shrinking per-chiplet yield gain se zyada ho jaata hai, toh ek sweet spot hota hai, "chhota hamesha better" nahi.