2.5D packaging and interposers: Exercises — Hardware deep dive

This page is a self-test ladder. Cover the solution, try the problem, then reveal. Each level climbs one rung of difficulty. Parent note: 2.5D Packaging and Interposers.

Before you start, here is the toolkit every problem draws on — nothing here is used before it is defined.

Level 1 — Recognition

L1.1

True or false, and say why: "In a 2.5D package the active chiplets are stacked on top of each other."

Recall Solution

False. In 2.5D the active chiplets sit side-by-side (a 2D layout). The only thing "below" them is the passive interposer, which carries wiring but does no computation. Vertical stacking of active dies is 3D, not 2.5D. See the parent note.

L1.2

Match each term to its one-line role: chiplet, interposer, microbump, TSV.

Recall Solution

Chiplet — a small, independently-fabricated die implementing part of the system.
Interposer — passive silicon substrate under the chiplets carrying dense short wiring.
Microbump — tiny solder joint (~40–50 µm pitch) between chiplet and interposer.
TSV (Through-Silicon Via) — a vertical copper via passing through the silicon thickness to the package below.

L1.3

Which formula predicts energy per bit, and which predicts total bandwidth?

Recall Solution

Energy per bit: $E_{bi t} = \frac{1}{2} c L V^{2}$ .
Total bandwidth: $B W = N_{w i r es} \times f$ .

Level 2 — Application

L2.1

A die has area $A = 2 cm^{2}$ on a wafer with defect density $D = 0.4 defects/cm^{2}$ . What is its yield?

Recall Solution

$Y = e^{- D A} = e^{- 0.4 \times 2} = e^{- 0.8} \approx 0.449$ So about 44.9% of these dies come out good. Why this formula? Zero-defect probability for a Poisson mean of $D A = 0.8$ .

L2.2

An interposer wire is $L_{in t} = 0.2 mm$ long; a PCB trace doing the same job is $L_{P C B} = 20 mm$ . Assume the same $c$ and $V$ . By what factor does the interposer cut energy per bit?

Recall Solution

Energy is $E_{bi t} = \frac{1}{2} c L V^{2}$ , so with $c$ and $V$ fixed, $E \propto L$ . Therefore $\frac{E _{in t}}{E _{P C B}} = \frac{L _{in t}}{L _{P C B}} = \frac{0.2}{20} = 0.01.$ The interposer uses 1% of the energy — a 100× reduction. Why only the length ratio matters: everything else cancels.

L2.3

An interposer routes $N_{w i r es} = 1024$ signal wires, each running at $f = 3 \times 1 0^{9}$ transfers/s. What is the total bandwidth in bits/s, and in GB/s?

Recall Solution

$B W = N_{w i r es} \times f = 1024 \times 3 \times 1 0^{9} = 3.072 \times 1 0^{12} bits/s .$ Convert to bytes (÷8): $3.072 \times 1 0^{12} /8 = 3.84 \times 1 0^{11} bytes/s = 384 GB/s$ (using $1 GB = 1 0^{9}$ bytes).

Level 3 — Analysis

L3.1

Take $D = 0.5 defects/cm^{2}$ . Compare a monolithic die of $A = 4 cm^{2}$ against four chiplets of $A = 1 cm^{2}$ each. Compute the yield of each, then the probability that all four chiplets are simultaneously good.

Look at the figure: the big square is the monolithic die; the four small squares are the chiplets. Red dots are random defects.

Recall Solution

Monolithic: $Y_{m o n o} = e^{- 0.5 \times 4} = e^{- 2} \approx 0.135$ → 13.5%. One chiplet: $Y_{c hi p} = e^{- 0.5 \times 1} = e^{- 0.5} \approx 0.607$ → 60.7%. All four good (independent dies): $Y_{c hi p}^{4} = e^{- 0.5 \times 4} = e^{- 2} \approx 0.135$ — same as the big die! The insight: the chance of getting four perfect chiplets in one draw equals the big die's yield, because total area is the same. The real win is that we do not need all four from the same draw — we bin good chiplets from many wafers and assemble only the good ones, discarding one $1 cm^{2}$ reject instead of one $4 cm^{2}$ reject. Per-defect wasted silicon drops 4×.

L3.2

Two schemes carry the same 512 wires between two chiplets. Scheme A is a silicon interposer at $1 μ m$ pitch; scheme B is a PCB at $100 μ m$ pitch. How much edge length (in mm) does each need to line up all 512 wires side by side?

Recall Solution

Edge length = (number of wires) × (pitch).

Interposer: $512 \times 1 μ m = 512 μ m = 0.512 mm$ .
PCB: $512 \times 100 μ m = 51200 μ m = 51.2 mm$ . The PCB needs a 100× longer chip edge — physically impossible for a ~5 mm chiplet edge. This is why dense buses demand an interposer.

Level 4 — Synthesis

L4.1

An HBM stack needs a 1024-bit data bus plus ~700 control/power signals (≈1700 wires) at $f = 2 \times 1 0^{9}$ transfers/s, routed along a 5 mm chiplet edge. (a) What data-bus bandwidth does 1024 bits at 2 GT/s give, in GB/s? (b) At what pitch (µm) must you route 1700 wires to fit them along 5 mm? (c) Can a 100 µm PCB do it? Can a 1 µm interposer?

Recall Solution

(a) $B W = 1024 \times 2 \times 1 0^{9} = 2.048 \times 1 0^{12}$ bits/s. In bytes: $\div 8 = 2.56 \times 1 0^{11} B/s = 256 GB/s$ . (b) Required pitch $= \frac{5 mm}{1700} = \frac{5000 μ m}{1700} \approx 2.94 µm per wire$ . (c) PCB pitch is ~100 µm ≫ 2.94 µm → impossible. Interposer pitch is ~1 µm < 2.94 µm → fits comfortably. Hence every HBM product ships on a 2.5D interposer. See HBM.

L4.2

You must place $9 cm^{2}$ of logic. The reticle limit is $\approx 8.58 cm^{2}$ (858 mm²). With $D = 0.3 defects/cm^{2}$ , compare: (a) is a monolithic $9 cm^{2}$ die even printable? (b) split into three $3 cm^{2}$ chiplets — yield of each?

Recall Solution

(a) $9 cm^{2} = 900 mm^{2} > 858 mm^{2}$ reticle limit → cannot be printed in one exposure at all. The yield question is moot; it's physically un-manufacturable as a monolith. See reticle limit. (b) Each $3 cm^{2}$ chiplet ( $300 mm^{2} < 858 mm^{2}$ , printable): $Y = e^{- 0.3 \times 3} = e^{- 0.9} \approx 0.407$ → 40.7% good. Chiplets are the only option here — both the reticle limit and yield force the split.

Level 5 — Mastery

L5.1

Design trade-off. You can build a system as one monolithic die of area $A$ , or as $n$ equal chiplets each of area $A / n$ on an interposer. Defect density $D$ . (a) Write yield of the monolith and of one chiplet. (b) Show algebraically that as $n$ grows, each chiplet's yield $\to 1$ . (c) With $A = 4 cm^{2}$ , $D = 0.5$ , find the smallest integer $n$ making each chiplet's yield $\geq 0.90$ .

Recall Solution

(a) Monolith: $Y_{m o n o} = e^{- D A}$ . One chiplet of area $A / n$ : $Y_{1} = e^{- D A / n}$ . (b) As $n \to \infty$ , the exponent $- D A / n \to 0$ , and $e^{0} = 1$ . So $Y_{1} \to 1$ — tiny dies are almost always defect-free. (Intuition: a raindrop rarely lands on a postage stamp.) (c) Require $e^{- D A / n} \geq 0.90$ . Take $ln$ : $- \frac{D A}{n} \geq ln 0.90 = - 0.10536$ . So $\frac{D A}{n} \leq 0.10536$ , i.e. $n \geq \frac{D A}{0.10536} = \frac{0.5 \times 4}{0.10536} = \frac{2}{0.10536} \approx 18.98$ . Smallest integer: $n = 19$ . Check: $Y_{1} = e^{- 2/19} = e^{- 0.10526} \approx 0.9001 \geq 0.90$ . ✓

L5.2

Full-system reasoning. HBM at 256 GB/s per stack (from L4.1). A GPU uses 4 stacks. (a) Total memory bandwidth? (b) If each bit costs $E_{bi t} = \frac{1}{2} c L V^{2}$ with $c = 2 \times 1 0^{- 16} F/µm$ , $L = 200 μ m$ , $V = 0.4 V$ , find $E_{bi t}$ in joules and in femtojoules (fJ). (c) At 256 GB/s = $2.048 \times 1 0^{12}$ bit/s per stack, what wire-switching power does one stack's bus draw (assume every bit toggles)?

Recall Solution

(a) $4 \times 256 = 1024 GB/s = 1.024 TB/s$ . (b) $C = c L = 2 \times 1 0^{- 16} \times 200 = 4 \times 1 0^{- 14} F$ . $E_{bi t} = \frac{1}{2} C V^{2} = 0.5 \times 4 \times 1 0^{- 14} \times (0.4)^{2} = 0.5 \times 4 \times 1 0^{- 14} \times 0.16 = 3.2 \times 1 0^{- 15} J = 3.2 fJ$ . (c) Power = energy/bit × bits/s $= 3.2 \times 1 0^{- 15} \times 2.048 \times 1 0^{12} = 6.55 \times 1 0^{- 3} W \approx 6.55 mW$ per stack (this counts only wire charging — the point is how tiny it is thanks to short interposer wires). Related: wire scaling.

Connect the ideas

Recall One-line self-check

Why is 2.5D "both cheaper and faster than a giant monolith"? ::: Chiplets dodge the reticle limit and win on yield ( $Y = e^{- D A}$ ), while the interposer's short, dense wires cut $E_{bi t} = \frac{1}{2} c L V^{2}$ and multiply $B W = N f$ .