2.5D packaging and interposers: Exercises — Hinglish deep dive

6.5.2 · D4 · Hardware › Advanced & Emerging Architectures › 2.5D packaging and interposers

Yeh page ek self-test ladder hai. Solution ko cover karo, problem try karo, phir reveal karo. Har level ek rung upar chadta hai difficulty ka. Parent note: 2.5D Packaging and Interposers.

Shuru karne se pehle, yeh toolkit hai jo har problem mein use hoti hai — koi bhi cheez use hone se pehle define ki gayi hai.

Level 1 — Recognition

L1.1

True ya false, aur karan batao: "2.5D package mein active chiplets ek doosre ke upar stack hote hain."

Recall Solution

False. 2.5D mein active chiplets side-by-side baithe hote hain (ek 2D layout). Unke "neeche" sirf passive interposer hota hai, jo wiring carry karta hai lekin koi computation nahi karta. Active dies ki vertical stacking 3D hai, 2.5D nahi. Dekho the parent note.

L1.2

Har term ko uski one-line role se match karo: chiplet, interposer, microbump, TSV.

Recall Solution

Chiplet — ek chhota, independently-fabricated die jo system ka kuch hissa implement karta hai.
Interposer — chiplets ke neeche passive silicon substrate jo dense short wiring carry karta hai.
Microbump — chiplet aur interposer ke beech tiny solder joint (~40–50 µm pitch).
TSV (Through-Silicon Via) — ek vertical copper via jo silicon ki thickness ke through package ke neeche tak jaata hai.

L1.3

Kaun sa formula energy per bit predict karta hai, aur kaun sa total bandwidth?

Recall Solution

Energy per bit: $E_{bi t} = \frac{1}{2} c L V^{2}$ .
Total bandwidth: $B W = N_{w i r es} \times f$ .

Level 2 — Application

L2.1

Ek die ka area $A = 2 cm^{2}$ hai, wafer par defect density $D = 0.4 defects/cm^{2}$ hai. Uski yield kya hai?

Recall Solution

$Y = e^{- D A} = e^{- 0.4 \times 2} = e^{- 0.8} \approx 0.449$ Toh lagbhag 44.9% dies good nikalte hain. Yeh formula kyun? $D A = 0.8$ Poisson mean ke liye zero-defect probability.

L2.2

Ek interposer wire $L_{in t} = 0.2 mm$ lambi hai; wahi kaam karne wala ek PCB trace $L_{P C B} = 20 mm$ ka hai. Assume karo same $c$ aur $V$ . Interposer energy per bit ko kitne factor se kam karta hai?

Recall Solution

Energy hai $E_{bi t} = \frac{1}{2} c L V^{2}$ , toh $c$ aur $V$ fixed hone par, $E \propto L$ . Isliye $\frac{E _{in t}}{E _{P C B}} = \frac{L _{in t}}{L _{P C B}} = \frac{0.2}{20} = 0.01.$ Interposer 1% energy use karta hai — ek 100× reduction. Sirf length ratio kyun matter karta hai: baaki sab cancel ho jaata hai.

L2.3

Ek interposer $N_{w i r es} = 1024$ signal wires route karta hai, har ek $f = 3 \times 1 0^{9}$ transfers/s par chal raha hai. Total bandwidth bits/s mein aur GB/s mein kya hai?

Recall Solution

$B W = N_{w i r es} \times f = 1024 \times 3 \times 1 0^{9} = 3.072 \times 1 0^{12} bits/s .$ Bytes mein convert karo (÷8): $3.072 \times 1 0^{12} /8 = 3.84 \times 1 0^{11} bytes/s = 384 GB/s$ ( $1 GB = 1 0^{9}$ bytes use karke).

Level 3 — Analysis

L3.1

Lo $D = 0.5 defects/cm^{2}$ . Compare karo ek monolithic die $A = 4 cm^{2}$ ki against chaar chiplets $A = 1 cm^{2}$ har ek. Har ek ki yield compute karo, phir probability ki chaaon chiplets ek saath good hain.

Figure dekho: bada square monolithic die hai; chaar chhote squares chiplets hain. Red dots random defects hain.

Recall Solution

Monolithic: $Y_{m o n o} = e^{- 0.5 \times 4} = e^{- 2} \approx 0.135$ → 13.5%. Ek chiplet: $Y_{c hi p} = e^{- 0.5 \times 1} = e^{- 0.5} \approx 0.607$ → 60.7%. Chaaon good (independent dies): $Y_{c hi p}^{4} = e^{- 0.5 \times 4} = e^{- 2} \approx 0.135$ — bade die ke same! Insight: ek hi draw mein chaar perfect chiplets milne ki chance bade die ki yield ke barabar hai, kyunki total area same hai. Asli fayda yeh hai ki hamen chaaon ek hi draw se nahi chahiye — hum good chiplets kai wafers se bin karte hain aur sirf good wale assemble karte hain, ek $1 cm^{2}$ reject discard karte hain ek $4 cm^{2}$ reject ki jagah. Per-defect wasted silicon 4× kam ho jaata hai.

L3.2

Do schemes 512 wires carry karte hain do chiplets ke beech. Scheme A ek silicon interposer hai $1 μ m$ pitch par; scheme B ek PCB hai $100 μ m$ pitch par. Saare 512 wires side by side line up karne ke liye har ek ko kitni edge length (mm mein) chahiye?

Recall Solution

Edge length = (wires ki sankhya) × (pitch).

Interposer: $512 \times 1 μ m = 512 μ m = 0.512 mm$ .
PCB: $512 \times 100 μ m = 51200 μ m = 51.2 mm$ . PCB ko 100× lamba chip edge chahiye — ek ~5 mm chiplet edge ke liye physically impossible. Isliye dense buses ke liye interposer zaroori hai.

Level 4 — Synthesis

L4.1

HBM stack ko 1024-bit data bus plus ~700 control/power signals (≈1700 wires) chahiye $f = 2 \times 1 0^{9}$ transfers/s par, 5 mm chiplet edge ke saath route hoke. (a) 1024 bits at 2 GT/s se kya data-bus bandwidth milti hai, GB/s mein? (b) Kis pitch (µm) par 1700 wires route karni padengi 5 mm mein fit karne ke liye? (c) Kya 100 µm PCB yeh kar sakta hai? Kya 1 µm interposer kar sakta hai?

Recall Solution

(a) $B W = 1024 \times 2 \times 1 0^{9} = 2.048 \times 1 0^{12}$ bits/s. Bytes mein: $\div 8 = 2.56 \times 1 0^{11} B/s = 256 GB/s$ . (b) Required pitch $= \frac{5 mm}{1700} = \frac{5000 μ m}{1700} \approx 2.94 µm per wire$ . (c) PCB pitch ~100 µm ≫ 2.94 µm → impossible. Interposer pitch ~1 µm < 2.94 µm → aasaani se fit. Isliye har HBM product 2.5D interposer par ship hota hai. Dekho HBM.

L4.2

Tumhe $9 cm^{2}$ logic place karni hai. Reticle limit $\approx 8.58 cm^{2}$ (858 mm²) hai. $D = 0.3 defects/cm^{2}$ ke saath compare karo: (a) kya monolithic $9 cm^{2}$ die printable bhi hai? (b) teen $3 cm^{2}$ chiplets mein split karo — har ek ki yield?

Recall Solution

(a) $9 cm^{2} = 900 mm^{2} > 858 mm^{2}$ reticle limit → ek hi exposure mein print hi nahi ho sakta. Yield ka sawal bekar hai; yeh physically un-manufacturable hai monolith ke roop mein. Dekho reticle limit. (b) Har $3 cm^{2}$ chiplet ( $300 mm^{2} < 858 mm^{2}$ , printable): $Y = e^{- 0.3 \times 3} = e^{- 0.9} \approx 0.407$ → 40.7% good. Chiplets yahan single option hain — reticle limit aur yield dono split force karte hain.

Level 5 — Mastery

L5.1

Design trade-off. Aap ek system area $A$ ki ek monolithic die ke roop mein bana sakte ho, ya $n$ equal chiplets mein har ek area $A / n$ ka, interposer par. Defect density $D$ . (a) Monolith ki aur ek chiplet ki yield likho. (b) Algebraically dikhao ki jaise $n$ badhta hai, har chiplet ki yield $\to 1$ . (c) $A = 4 cm^{2}$ , $D = 0.5$ ke saath, sabse chhota integer $n$ dhundho jisse har chiplet ki yield $\geq 0.90$ ho.

Recall Solution

(a) Monolith: $Y_{m o n o} = e^{- D A}$ . Area $A / n$ wala ek chiplet: $Y_{1} = e^{- D A / n}$ . (b) Jaise $n \to \infty$ , exponent $- D A / n \to 0$ , aur $e^{0} = 1$ . Toh $Y_{1} \to 1$ — tiny dies almost hamesha defect-free hoti hain. (Intuition: raindrop rarely kisi postage stamp par girti hai.) (c) Chahiye $e^{- D A / n} \geq 0.90$ . $ln$ lo: $- \frac{D A}{n} \geq ln 0.90 = - 0.10536$ . Toh $\frac{D A}{n} \leq 0.10536$ , yaani $n \geq \frac{D A}{0.10536} = \frac{0.5 \times 4}{0.10536} = \frac{2}{0.10536} \approx 18.98$ . Sabse chhota integer: $n = 19$ . Check: $Y_{1} = e^{- 2/19} = e^{- 0.10526} \approx 0.9001 \geq 0.90$ . ✓

L5.2

Full-system reasoning. HBM at 256 GB/s per stack (L4.1 se). Ek GPU 4 stacks use karta hai. (a) Total memory bandwidth? (b) Agar har bit ka cost $E_{bi t} = \frac{1}{2} c L V^{2}$ hai, $c = 2 \times 1 0^{- 16} F/µm$ , $L = 200 μ m$ , $V = 0.4 V$ ke saath, toh $E_{bi t}$ joules mein aur femtojoules (fJ) mein dhundho. (c) 256 GB/s = $2.048 \times 1 0^{12}$ bit/s per stack par, ek stack ka bus kitna wire-switching power draw karta hai (assume karo har bit toggle hoti hai)?

Recall Solution

(a) $4 \times 256 = 1024 GB/s = 1.024 TB/s$ . (b) $C = c L = 2 \times 1 0^{- 16} \times 200 = 4 \times 1 0^{- 14} F$ . $E_{bi t} = \frac{1}{2} C V^{2} = 0.5 \times 4 \times 1 0^{- 14} \times (0.4)^{2} = 0.5 \times 4 \times 1 0^{- 14} \times 0.16 = 3.2 \times 1 0^{- 15} J = 3.2 fJ$ . (c) Power = energy/bit × bits/s $= 3.2 \times 1 0^{- 15} \times 2.048 \times 1 0^{12} = 6.55 \times 1 0^{- 3} W \approx 6.55 mW$ per stack (yeh sirf wire charging count karta hai — point yeh hai ki short interposer wires ki wajah se yeh kitna chhota hai). Related: wire scaling.

Connect the ideas

Recall One-line self-check

2.5D "ek giant monolith se sasta aur tez dono" kyun hai? ::: Chiplets reticle limit se bachte hain aur yield mein jeet jaate hain ( $Y = e^{- D A}$ ), jabki interposer ki short, dense wires $E_{bi t} = \frac{1}{2} c L V^{2}$ kam karti hain aur $B W = N f$ multiply karti hain.