Worked examples — 2.5D packaging and interposers

6.5.2 · D3 · Hardware › Advanced & Emerging Architectures › 2.5D packaging and interposers

Yeh page 2.5D packaging and interposers ka drill floor hai. Parent note ne tumhe tools diye; yahan hum unhe har possible case mein run karte hain — bade dies aur chote dies, zero aur infinity defect densities, energy comparisons, bandwidth budgets, ek real-world word problem, aur ek exam-style trap.

Numbers se pehle, ek promise: neeche use kiya gaya har symbol ya toh parent note define karta hai ya yahan re-define kiya gaya hai. Agar tum $Y$, $D$, $A$, $c$, $L$, $V$, $N$, $f$ pehli baar dekh rahe ho, toh is line ke neeche wali table batati hai ki har ek ka kya matlab hai.

Do master formulas jo hum har jagah reuse karte hain (parent se):

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The scenario matrix

Neeche har worked example is matrix ke cell ke saath tagged hai jise wo cover karta hai. Saath milke yeh sab cells ko touch karte hain.

Cell	Kya vary karta hai	"Edge" jo hum test karte hain
C1 Small area	$A$ small	Yield near 1 — chiplet regime
C2 Large area	$A$ large	Yield collapse — monolithic regime
C3 Zero defects	$D=0$	Degenerate: $Y=1$, chiplets se koi yield benefit nahi
C4 Huge defects	$D\to \infty$	Limiting: $Y\to 0$, kuch nahi bachta
C5 Split-vs-whole	fixed total $A$, zyada cuts	Kitne chiplets "enough" hain?
C6 Energy ratio	$L,c$ change	Interposer vs PCB energy per bit
C7 Bandwidth budget	$N,f$	Kya bus fit hoti hai? (word problem)
C8 Exam twist	mixed	Overhead costs / jab 2.5D haare

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C1 + C2 — Yield dono extremes par

1. Chota area plug karo. $Y_a=e^{-0.4\times 0.5}=e^{-0.2}$. Yeh step kyun? $Y=e^{-DA}$ die par zero defects hone ki probability hai; chota $A$ ⇒ chota exponent ⇒ $Y$ near 1.
2. Evaluate karo: $e^{-0.2}\approx 0.8187$ → ≈ 81.9% good.
3. Bada area plug karo. $Y_b=e^{-0.4\times 8}=e^{-3.2}$. Yeh step kyun? Same formula; bada $A$ ⇒ bada exponent ⇒ $Y$ 0 ki taraf crush ho jaata hai.
4. Evaluate karo: $e^{-3.2}\approx 0.0408$ → ≈ 4.1% good.

Recall Area itni violently kyun hurt karta hai?

Kyunki area exponent mein hota hai. Area double karne se yield half nahi hoti — yeh survival penalty ko square kar deta hai. Yahi exponential chiplets ke exist karne ki poori economic reason hai.

Verify: exponents $-0.2$ aur $-3.2$ ka sign sahi hai (negative → $Y<1$). Tiny die (81.9%) giant (4.1%) ko ~20× se beat karta hai, jo "chote dies defects se bachte hain" intuition se match karta hai.

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C3 + C4 — Degenerate limits

1. Zero-defect case. $Y=e^{-0\times A}=e^0=1$ kisi bhi $A$ ke liye. Yeh step kyun? Agar koi defects kabhi nahi girte, toh har die — badi ya choti — perfect hai. Exponent vanish ho jaata hai.
2. Consequence: jab $D=0$, chiplets zero yield advantage dete hain. 2.5D ke liye yield argument sirf isliye exist karta hai kyunki $D>0$ hota hai. (2.5D phir bhi reticle limit aur node-mixing par win kar sakta hai, lekin yahan yield par nahi.)
3. Huge-defect case. $Y=e^{-10\times 1}=e^{-10}\approx 4.54\times 10^{-5}$. Yeh step kyun? Defects ki large mean number ⇒ near-certain ki kam se kam ek toh girega ⇒ almost kuch nahi bachta.
4. Limit check: jaise $D\to \infty$, $e^{-DA}\to 0$. Koi bhi packaging trick ek broken fab ko nahi bachaa sakti.

Verify: $D=0\Rightarrow e^0=1$ ($A$ se independent, correct degenerate behaviour). $e^{-10}\approx 4.5\times 10^{-5}$ ek tiny positive number hai — kabhi exactly zero nahi, toh even ek bad fab kuch silicon yield karta hai, jaise physics demand karta hai.

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C5 — Kitne chiplets "enough" hain?

1. Per-chiplet area hai $A_n=4/n$. Per-chiplet yield $y_n=e^{-0.5\cdot 4/n}=e^{-2/n}$. Yeh step kyun? System ko $n$ pieces mein cut karne se har piece ki area shrink hoti hai, jo har piece ki individual survival probability badhata hai.
2. Monolith $n=1$: $y_1=e^{-2}\approx 0.135$ → 13.5% whole chips good.
3. 4 chiplets $n=4$: $y_4=e^{-0.5}\approx 0.607$ → har chiplet 60.7% good.
4. 16 chiplets $n=16$: $y_{16}=e^{-0.125}\approx 0.882$ → har chiplet 88.2% good. Yeh step kyun? Jaise $n$ badhta hai, exponent $-2/n\to 0$, toh $y_n\to 1$ — har tiny die near-perfect ho jaata hai.
5. The catch (infinite chiplets kyun nahi?): har extra cut microbumps, interposer wiring, aur assembly cost add karta hai. Individual dies ki yield diminishing return ke saath badhti rehti hai, jabki packaging overhead linearly badhta hai. Woh trade-off — sirf yield nahi — sweet spot set karta hai (practice mein usually 2–8 chiplets, dekho Chiplets and Heterogeneous Integration).

Recall

$e^{-2/n}$ kya approach karta hai jaise $n\to \infty$? ${\lim }_{n\to \infty }{e}^{-2/n}=e^0=1$. Individual yield 1 par saturate ho jaati hai — pure diminishing returns.

Verify: sequence $0.135,0.607,0.882$ strictly increase karta hai 1 ki taraf jaise $n$ badhta hai, aur har ek $e^{-2/n}$ ke equal hai. Gaps shrink hoti hain ($0.607-0.135=0.472$ vs $0.882-0.607=0.275$) — diminishing returns confirm karta hai.

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C6 — Energy per bit: interposer vs PCB

1. Energy formula. $E_{bit}=\frac{1}{2}cL{V}^2$. Yeh step kyun? Ek bit bhejna matlab wire ki capacitance ko $V$ tak charge karna; ek capacitor ki charging energy $\frac{1}{2}C{V}^2$ hoti hai jisme $C=cL$.
2. $V^2$ ek baar compute karo. $V^2=0.8^2=0.64{\text{V}}^2$. Yeh step kyun? Dono cases same voltage share karte hain, toh re-work se bachne ke liye ise factor out karo.
3. PCB: $E_{PCB}=\frac{1}{2}(2\times 10^{-10})(0.020)(0.64)=1.28\times 10^{-12}\text{J}$ = 1.28 pJ/bit.
4. Interposer: $E_{int}=\frac{1}{2}(2\times 10^{-10})(0.0002)(0.64)=1.28\times 10^{-14}\text{J}$ = 0.0128 pJ/bit.
5. Ratio. $E_{int}/E_{PCB}=L_{int}/L_{PCB}=0.2/20=0.01$ → 100× kam energy. Yeh step kyun? Jab $c$ aur $V$ identical hain, energy purely length ke proportional hai, toh ratio length ratio hai. (Reality mein interposer ki finer geometry $c$ bhi lower karti hai, jisse win aur bada ho jaata hai.)

Verify: units — $\text{F/m}\times \text{m}\times {\text{V}}^2=\text{F}\cdot {\text{V}}^2=\text{J}$ ✓. Numbers: $1.28\text{ pJ}$ vs $0.0128\text{ pJ}$, ratio exactly $0.01$. ✓

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C7 — Bandwidth budget (real-world word problem)

1. Raw bandwidth in bits/s. $BW=N\times f=1024\times 3.2\times 10^9=3.2768\times 10^{12}\text{bits/s}$. Yeh step kyun? Bandwidth lanes × per-lane rate hai; 1024 wires mein se har ek per second $f$ transfers carry karta hai, har ek 1 bit ka.
2. Bytes/s mein convert karo. 8 se divide karo: $3.2768\times 10^{12}/8=4.096\times 10^{11}\text{B/s}=$ 409.6 GB/s. Yeh step kyun? Storage/bandwidth targets bytes mein quote kiye jaate hain (8 bits = 1 byte).
3. Target meet kiya? $409.6\text{GB/s}\ge 300\text{GB/s}$ → haan, comfortably.
4. Kya PCB 1024 wires route kar sakta hai? PCB pitch ~100 µm par, 1024 wires ko data ke liye ~$1024\times 100\mu \text{m}=102.4\text{mm}$ edge chahiye — ~5 mm die edge ke saath impossible. Interposer pitch ~1 µm par, inhe sirf ~1 mm edge chahiye. Yeh step kyun? Parallelism se bandwidth useless hai agar tum physically wires place nahi kar sakte; yahi exact reason hai ki HBM ek interposer par ship hoti hai. Dekho High Bandwidth Memory (HBM).

Recall PCB HBM ki bus kyun carry nahi kar sakta?

1024 wires at 100 µm pitch ⇒ ~102 mm routing edge; die edge sirf kuch mm hoti hai. Sirf ~1 µm interposer pitch inhe fit karta hai.

Verify: $1024\times 3.2\times 10^9=3.2768\times 10^{12}$ bits/s; ÷8 = $4.096\times 10^{11}$ B/s = 409.6 GB/s ≥ 300 ✓. PCB edge needed $1024\times 100\mu \text{m}=0.1024\text{ m}=102.4\text{ mm}$ ✓.

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C8 — Exam twist: 2.5D kab haarta hai?

1. Monolith yield. $Y_{mono}=e^{-0.2\times 1}=e^{-0.2}\approx 0.8187$. Yeh step kyun? Single die ka baseline good-fraction.
2. Cost per good monolith ("area units" mein) $=A/Y=1/0.8187\approx 1.2215$. Yeh step kyun? Agar sirf 81.9% bachte hain, toh ek acha paane ke liye tumhe $1/0.819$ dies-worth area fabricate karni padegi.
3. Chiplet yield. har chiplet $y=e^{-0.2\times 0.5}=e^{-0.1}\approx 0.9048$; ek system ko dono achha chahiye: $Y_{sys}=y^2=e^{-0.2}\approx 0.8187$. Yeh step kyun? Do independent dies ko dono pass karna hoga; probabilities multiply karo. Notice karo $y^2=e^{-0.1\cdot 2}=e^{-0.2}$ — monolith ke identical total silicon-yield, kyunki total area unchanged hai!
4. Chiplet cost overhead ke saath. Good silicon per system $=1/0.8187\approx 1.2215$, phir 40% packaging tax apply karo: $1.2215\times 1.4\approx 1.710$. Yeh step kyun? Interposer aur assembly real costs hain jo monolith nahi pay karta.
5. Compare karo. Monolith 1.2215 vs chiplet 1.710 → monolith yahan sasta hai. Yeh trap kyun kaam karta hai: chote area par, split karne se yield gain tiny hota hai (dono $e^{-0.2}$ dete hain), toh 40% overhead dominate karta hai. Chiplets sirf tab jeetate hain jab $A$ large ho (C2) aur yield gain overhead ko outweigh kare.

Verify: monolith cost $1/e^{-0.2}=e^{0.2}\approx 1.2214$; chiplet total yield $e^{-0.1\cdot 2}=e^{-0.2}$ (monolith ke equal), cost $e^{0.2}\times 1.4\approx 1.710$; $1.710>1.221$ toh monolith jeet jaata hai ✓.

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Recap: kis cell ne kya sikhaya

Recall Matrix fill karo

C1/C2 — yield near 1 vs collapsed, sab exponent se ::: Chota $A$ ⇒ $Y\approx 0.82$; bada $A$ ⇒ $Y\approx 0.04$. Area exponent mein rehta hai. C3 — $D=0$ implication ::: $Y=1$ kisi bhi area ke liye; chiplets zero yield benefit dete hain. C4 — $D\to \infty$ limit ::: $Y\to 0$; koi bhi packaging broken fab ko nahi bachata. C6 — energy ratio equal hai ::: length ratio ke (jab $c,V$ match karte hain): 100× shorter wire ⇒ 100× kam energy. C7 — HBM ko interposer kyun chahiye ::: 1024 wires PCB pitch par fit nahi hoti; sirf ~1 µm interposer pitch inhe route karta hai. C8 — chiplets kab haarte hain ::: Jab area chota ho, yield gain tiny hota hai aur packaging overhead dominate karta hai.

Related builds: Wafer Yield and Defect Density, Reticle Limit and Lithography, 3D Stacking and TSVs, Moore's Law and its Slowdown, Package Substrate and Ball Grid Array.