Model defects as random points scattered on the wafer with density D0 (defects per mm²). A die survives only if zero defects land on it. If defects follow a Poisson process, the probability of k defects on area A is:
P(k)=k!(D0A)ke−D0A
Why Poisson? Defects are rare, independent, spatially uniform events — exactly the Poisson setup.
Yield = probability of zero defects, i.e. k=0:
Y=P(0)=e−D0A
Why this step? Plug k=0: (D0A)0=1 and 0!=1, leaving only e−D0A.
Now split one big die of area A into N chiplets each of area A/N. The yield per chiplet is:
Ychiplet=e−D0A/N
Each chiplet is individually more likely to be good. We test and discard bad ones ("known-good die", KGD) before assembly, so we only pay to package good silicon.
Interposer — a passive (or active) slab (often silicon) that carries dense wiring between dies sitting on top of it (2.5D).
Silicon bridge — a small silicon chip embedded in the substrate connecting the edges of two neighbouring dies (e.g. Intel EMIB) — cheaper than a full interposer.
TSV (Through-Silicon Via) — a vertical copper via drilled through a die so signals pass top-to-bottom (needed for 3D stacking).
Die-to-die (D2D) interface — the protocol + physical layer chiplets speak over, e.g. the UCIe standard (Universal Chiplet Interconnect Express).
Bandwidth per unit area scales with how many wires you can pack, and short wires can run fast with low energy. Interconnect energy roughly scales with distance:
Ebit∝C⋅V2,C∝L
Why? A wire's capacitance C grows with its length L; charging it each bit costs 21CV2. Shorter die-to-die links (µm scale on-package) cost far less energy per bit than going off-package to a PCB trace (cm scale).
Defects are ~uniform random; yield Y=e−D0A falls exponentially with area, so bigger dies catch more defects.
State the Poisson yield model and its assumption.
Y=e−D0A; assumes defects are rare, independent, uniformly distributed (Poisson process), and die is good iff zero defects.
What is a chiplet?
A small, independently manufactured die implementing part of a system, combined with other dies in one package.
Difference between 2.5D and 3D integration?
2.5D = dies side-by-side wired through an interposer/bridge below them; 3D = dies stacked vertically wired through TSVs.
What is a TSV and why needed?
Through-Silicon Via — a vertical conductor through a die enabling signals to pass top-to-bottom; required for 3D stacking.
What is UCIe?
Universal Chiplet Interconnect Express — a standard die-to-die interface (protocol + physical layer) for interoperable chiplets.
Why do short die-to-die links save energy?
Ebit=21CV2 and C∝L; shorter wires have less capacitance, so less energy per bit.
Name two reasons chiplets can be worse than monolithic.
Added packaging/assembly/test cost, plus duplicated D2D I/O area & power — bad when die is small (already high yield).
What is the reticle limit and why does it matter?
~858 mm² max area lithography can pattern in one exposure; you can't print a monolithic die larger than this.
Why is heat a problem in 3D stacking?
Stacked dies heat each other, raising power density (W/mm²); the bottom die's heat must pass through the top, limiting cooling.
When do chiplets win economically?
Large monolithic area (poor yield), need to mix process nodes, or reuse the same die across products.
Recall Feynman: explain to a 12-year-old
Imagine baking cookies on a giant sheet, but sometimes a raisin (defect) falls randomly. If you bake one huge cookie, a single raisin ruins the whole thing — very wasteful. If you bake many small cookies, one bad raisin ruins only one small cookie; you throw that one out and keep the rest. Chiplets are the small cookies: we bake little chips, taste-test each one, keep only the good ones, then glue them together into one "super cookie" package. Gluing them close together lets them talk fast without wasting energy — but stacking them on top makes them hot, like cookies steaming each other.
Dekho, problem simple hai: agar tum ek bahut bada chip (monolithic die) banao, to silicon pe jo random defects hote hain, unme se koi ek bhi tumhare bade die pe aa gaya to poora die kharab. Yield formula hai Y=e−D0A — yani area jitna bada, yield utni tezi se girti hai (exponentially). Isliye ek 800 mm² ka die shayad sirf 1.8% baar theek nikle. Waste bahut zyada.
Solution: bade die ko chhote chiplets me tod do. Har chhota die alag se banao, test karo, aur sirf good ones ko package ke andar jodo. 200 mm² wale chiplet ki yield ~37% aa jati hai — bahut behtar. Bonus: alag-alag chiplets alag process node pe ban sakte hain (logic latest node pe, IO/analog purane sasta node pe).
Jodne ke do tareeke hain. 2.5D me dies ek doosre ke bagal me rakhte hain aur unke neeche ek interposer (ya silicon bridge) se dense wiring karte hain. 3D me dies ek doosre ke upar stack karte hain aur TSV (through-silicon via) se signal upar-neeche jaate hain. Chhoti wire ka matlab kam capacitance (Ebit=21CV2, aur C∝L), isliye bandwidth zyada aur energy kam. Lekin 3D me garmi phas jaati hai — heat nikalna mushkil ho jaata hai.
Yaad rakho: chiplets har jagah sasta nahi. Packaging, TSV, extra testing ka kharcha hai. Jab die chhota ho aur yield already achi ho, to monolithic hi behtar. Chiplets tab jeette hain jab area bada ho, ya nodes mix karne ho, ya same die reuse karna ho. Yehi 80/20 baat hai.
