Before you can spot a trap, you must own the two models the traps are built on. So we build them from zero first — pictures before symbols — then quiz.
Every formula on this page carries the letter e. Before using it we earn it.
Why does e show up in yield? Because "the chance of surviving a little more area is proportional to how likely you already are to have survived" — that proportional-shrinking rule is exactly what e−stuff describes.
Look at the curve above: at exponent 0 the value is 1 (100%), and as the exponent grows negative the value slides toward — but never touches — the floor at 0. That shape ise−x, and it is the skeleton of the yield model.
The parent note asserts Y=e−D0A "because Poisson." Here is the actual reasoning, built by hand.
The chance one tile is clean is (1−p). With M independent tiles, the chance all are clean is:
Y=(1−p)M=(1−MD0A)M
Why now take M→∞? Tiles are an artificial grid; the true die has no tiles, so we shrink them to points (M→∞). There is a famous limit that says exactly this expression collapses to an exponential:
limM→∞(1−Mx)M=e−x
Setting x=D0A gives Y=e−D0A. That limit is precisely where the e comes from — the Poisson "zero-events" probability is the continuous version of "no tile got hit."
The plot above draws Y against area A and marks the three edge cases you will be quizzed on: the curve starts at 1 when A=0, sinks toward 0 as A→∞, and the dashed flat line at the top is what happens when D0=0 (yield stays 1 forever). See the splitting: one huge die sits deep in the doomed zone; four small dies each sit high on the curve.
The energy model uses C∝L without proof. Here is why capacitance grows linearly with length.
Now the energy. Sending one bit means charging that wire's capacitance up to voltage V:
Ebit=21CV2∝L
Why V2 and not V? Charging a capacitor is like lifting sand into a bin: the first charge slips in for free (empty bin, no back-pressure), the last charge must be pushed against the full voltage already there. Averaging the growing back-pressure gives the factor 21, and because both the amount of charge and the voltage you push it against grow with V, the energy scales as V×V=V2.
The left panel shows energy climbing linearly with wire length L — this is why an off-package cm-scale trace (far right) costs orders of magnitude more than an on-package µm-scale link (far left). The right panel shows energy climbing as a parabola in voltage V — steeper, because it is squared. Two knobs, two different shapes: memorise which is which.
The thumbnail above grounds the adjacent topics you'll see linked: a 2.5D layout (dies side-by-side on an interposer beneath), a 3D stack (dies on top, vertical TSVs through them), and the short-vs-long link that drives interconnect energy and feeds memory bandwidth.
Splitting a big die into N chiplets multiplies total good silicon per wafer without any downside.
False. Per-chiplet yield rises (e−D0A/N), but you now pay for packaging, interposer/bridge area, extra test, and duplicated die-to-die I/O — real costs the monolith never had.
The yield formula Y=e−D0A says a die with zero area has yield 1.
True, and it's a sanity check.A=0⇒e0=1: a die occupying no silicon can catch no defects, so it is certainly "good" — the model behaves correctly at the degenerate limit.
If you shrink a die's area to a quarter, its yield roughly quadruples.
False — the relationship is exponential, not linear. Yield goes from e−D0A to e−D0A/4; the ratio is e3D0A/4, which depends on how bad the original yield was, not a fixed factor of 4.
Two chiplets stacked in 3D always have lower total latency than the same two placed side-by-side in 2.5D.
False in general. Wires are shorter in 3D so link latency drops, but thermal throttling can force lower clocks, and TSV routing adds its own overhead — "shorter wire" is not the whole latency story.
A monolithic die and a 4-chiplet version made of the same total area remove exactly the same number of defective transistors from use.
False. In the chiplet case a defect only kills its own small die (which you discard); in the monolith one defect condemns the whole large die. Same defects, very different amount of wasted good silicon.
UCIe is a physical connector you can plug and unplug.
False. UCIe (Universal Chiplet Interconnect Express) is a die-to-die standard — a protocol plus physical-layer spec — that lets chiplets from different vendors interoperate; it is fabricated into the dies, not a socket.
Interconnect energy per bit depends on the voltage more sharply than on the wire length.
True per the model.Ebit=21CV2 is quadratic in V but only linear in L (through C∝L); halving voltage cuts energy ~4×, halving length only ~2×.
Below the reticle limit, going monolithic is impossible.
False — it is the opposite. The reticle limit (~858 mm²) is the maximum one exposure can pattern; below it monolithic is perfectly possible and often the cheaper choice for small, high-yield dies.
"A chiplet with area 200 mm² and D0=0.005 has yield e−0.005≈0.995."
The error is forgetting to multiply D0 by the area: yield is e−D0A=e−0.005×200=e−1≈0.368, not e−0.005.
"Chiplets let us mix process nodes because the interposer converts one node's signals into another's."
The interposer does no conversion — it is passive wiring. Mixing nodes works simply because each die is manufactured separately, so each can pick whatever node suits it (see Heterogeneous integration).
"3D stacking is better because the TSVs give more bandwidth than any 2.5D wire could."
TSVs give short vertical links, which is why 3D can hit high bandwidth — but the real driver is proximity (short L), and 2.5D can also be high-bandwidth; the claim overstates TSVs as the sole cause and ignores heat.
"Yield Y=e−D0A counts the probability of at most one defect, since chips can tolerate a few."
Wrong: it is the probability of exactly zero defects. The model treats a die as good iff no defect lands on it; tolerating defects (via redundancy) is a separate, more optimistic model.
"Because C∝L, an off-package PCB trace (cm) costs about the same energy per bit as an on-package link (µm)."
The opposite. Since Ebit∝L and cm is ~10⁴× longer than µm, off-package links cost orders of magnitude more energy per bit — the core reason to bring dies close (see Interconnect energy and dark silicon).
"Silicon bridges (like EMIB) are cheaper than full interposers because they use TSVs instead of wiring."
Backwards. A bridge is cheap precisely because it is a small silicon chip wiring only the edges of two dies — you avoid a large interposer and mostly avoid TSVs, not embrace them.
Why is the Poisson distribution — not, say, a bell curve — the right model for defects?
Because defects are rare, independent, spatially uniform events per unit area, which is exactly the tile-limit setup that produces e−D0A; a Gaussian would wrongly assume a symmetric spread around a mean count.
Why does the energy model use V2 rather than V?
Charging a capacitor to voltage V stores energy 21CV2; both the charge delivered and the voltage it is pushed against grow with V, so the energy scales as V×V, not linearly.
Why does wire capacitance grow linearly with length?
A wire is a chain of identical per-segment capacitors in parallel-add; doubling length doubles the segment count and hence C, so C∝L.
Why can chiplets be more expensive than a monolith for a small die?
A small die already has high monolithic yield, so splitting it saves almost nothing — yet you still pay full packaging, assembly, test, and duplicated die-to-die I/O overhead, which now dominates.
Why does 3D stacking make heat harder to manage than 2.5D?
Stacked dies sit directly on each other, so their heat must pass through neighbouring silicon; power density (W/mm²) rises and the buried die can't reach a heatsink easily, unlike side-by-side dies each with their own top surface.
Why does the industry favour logic-on-cache over logic-on-logic for 3D?
Cache (SRAM) is comparatively low-power, so stacking it on hot logic adds little heat; two hot logic dies stacked would compound power density and force aggressive throttling.
Why does moving computation to chiplets connect to the slowdown of Moore's Law?
When a single node can no longer cheaply shrink transistors and the reticle caps monolithic size, packaging many good small dies becomes the practical way to keep scaling system-level transistor count.
What does the yield model predict as die area A→∞?
Y=e−D0A→0: an infinitely large die is certain to catch a defect, so yield vanishes — the model correctly shows monolithic scaling collapses (see the curve dropping to the floor in figure s02).
What happens to yield if defect density D0=0 (a perfect process)?
Y=e0=1 for any area — with zero defects, size no longer matters (the flat dashed line in figure s02) and the whole chiplet-vs-monolith yield argument disappears; only reticle and node-mixing reasons remain.
If you split into N→∞ chiplets, does yield keep improving forever?
Per-chiplet yield e−D0A/N→1, but you must assemble all N correctly; assembly-failure and per-die I/O overhead grow with N, so total system yield and cost eventually worsen. There is an optimum N, not infinity.
For a die exactly at the reticle limit (~858 mm²), is chiplet splitting mandatory?
Not mandatory — you can still print it monolithically at the very edge of what one exposure allows; splitting becomes forced only when the design would exceed the limit and need imperfect stitching (see Wafer yield and defect density for why you'd want to split anyway).
If two chiplets need almost no data exchange, does bringing them physically close still help?
Barely — the Ebit∝L saving only matters for links you actually use heavily. With little traffic, cheap far-apart placement (or even separate packages) can be the better trade.
Recall One-sentence recap of the traps
Yield is exponential in area (not linear), the energy win is quadratic in voltage, linear in length, chiplets pay a packaging tax that only large or node-mixed designs earn back, and 3D's short wires come bundled with trapped heat.