Chiplets and multi-die integration: Question bank — Hinglish deep dive

6.5.1 · D5 · Hardware › Advanced & Emerging Architectures › Chiplets and multi-die integration

Kisi bhi trap ko pakadne se pehle, tumhare paas woh do models hone chahiye jinpe ye traps bane hain. Isliye hum unhe zero se build karte hain — pehle pictures, phir symbols — aur tab quiz lete hain.

Warm-up 0: yeh letter $e$ kya hai?

Is page ke har formula mein letter $e$ aata hai. Use karne se pehle hum ise samjhenge.

$e$ yield mein kyun aata hai? Kyunki "thodi aur area survive karne ka chance us baat ke proportional hai ki tum pehle se kitna survive kar chuke ho" — woh proportional-shrinking rule exactly $e^{- stuff}$ describe karta hai.

Upar wala curve dekho: exponent $0$ par value $1$ hai (100%), aur jaise jaise exponent negative hota jaata hai value $0$ ki taraf slide karti hai — lekin kabhi touch nahi karti. Woh shape hi $e^{- x}$ hai, aur yield model ka skeleton yehi hai.

Warm-up 1: defects Poisson process kyun dete hain, step by step

Parent note assert karta hai $Y = e^{- D_{0} A}$ "because Poisson." Yeh rahe actual reasoning, haath se build ki hui.

Ek tile ke clean hone ka chance $(1 - p)$ hai. $M$ independent tiles ke saath, sabke clean hone ka chance hai:

$Y = (1 - p)^{M} = (1 - \frac{D _{0} A}{M})^{M}$

Ab $M \to \infty$ kyun lete hain? Tiles ek artificial grid hain; asli die mein koi tiles nahi hain, isliye hum unhe points tak shrink karte hain ( $M \to \infty$ ). Ek famous limit hai jo kehta hai yeh expression exactly ek exponential mein collapse hoti hai:

$lim_{M \to \infty} (1 - \frac{x}{M})^{M} = e^{- x}$

$x = D_{0} A$ rakhne par $Y = e^{- D_{0} A}$ milta hai. Woh limit hi exactly woh jagah hai jahan se $e$ aata hai — Poisson "zero-events" probability "no tile got hit" ka continuous version hai.

Upar wala plot $Y$ ko area $A$ ke against draw karta hai aur teen edge cases mark karta hai jinke baare mein tumse quiz hoga: curve $A = 0$ par $1$ se start hoti hai, $A \to \infty$ par $0$ ki taraf jaati hai, aur upar wali dashed flat line dikhati hai kya hota hai jab $D_{0} = 0$ (yield hamesha $1$ rehti hai). Splitting dekho: ek bada die doomed zone mein gehre baithe hai; char chhote dies curve par upar baithe hain.

Warm-up 2: wire capacitance $C \propto L$ kyun hai, aur energy kahan jaati hai

Energy model bina proof ke $C \propto L$ use karta hai. Yeh hai kyun capacitance length ke saath linearly badhti hai.

Ab energy. Ek bit bhejna matlab us wire ki capacitance ko voltage $V$ tak charge karna:

$E_{bit} = \frac{1}{2} C V^{2} \propto L$

$V^{2}$ kyun, $V$ kyun nahi? Capacitor charge karna aise hai jaise bin mein sand uthana: pehla charge free mein jaata hai (khaali bin, koi back-pressure nahi), aakhri charge ko wahan already poori voltage ke against push karna padta hai. Badhte back-pressure ko average karne par $\frac{1}{2}$ factor milta hai, aur kyunki charge ki quantity aur jis voltage ke against push karo — dono $V$ ke saath badhte hain, energy $V \times V = V^{2}$ scale karti hai.

Left panel dikhata hai energy wire length $L$ ke saath linearly badhti hai — isliye ek off-package cm-scale trace (far right) ek on-package µm-scale link (far left) se orders of magnitude zyada costly hai. Right panel dikhata hai energy voltage $V$ mein parabola ki tarah badhti hai — steeper, kyunki squared hai. Do knobs, do alag shapes: yaad rakho kaun sa kaun sa hai.

Upar wala thumbnail adjacent topics ground karta hai jo tumhe linked milenge: ek 2.5D layout (dies side-by-side neeche ek interposer par), ek 3D stack (dies upar, unke through vertical TSVs), aur short-vs-long link jo interconnect energy drive karta hai aur memory bandwidth feed karta hai.

Warm-up 3: "reticle" aur "reticle limit" ka asli matlab

Yeh dhyan mein rakho: reticle limit ek maximum hai jise exceed nahi kar sakte, minimum nahi hai jise reach karna zaroori ho — neeche ek trap exactly usi confusion ko test karta hai.

True ya false — justify karo

Ek bade die ko

N

chiplets mein split karna wafer per total good silicon ko bina kisi downside ke multiply karta hai.

False. Per-chiplet yield badhti hai (

e^{- D_{0} A / N}

), lekin ab tum packaging, interposer/bridge area, extra test, aur duplicated die-to-die I/O ke liye pay karte ho — real costs jo monolith ne kabhi nahi uthaye.

Yield formula

Y = e^{- D_{0} A}

kehta hai zero area wale die ki yield 1 hogi.

True, aur yeh ek sanity check hai.

A = 0 \Rightarrow e^{0} = 1

: koi silicon occupy na karne wala die koi defect catch nahi kar sakta, isliye woh certainly "good" hai — model degenerate limit par sahi behave karta hai.

Agar die ki area quarter kar do, uski yield roughly quadruple ho jaati hai.

False — relationship exponential hai, linear nahi. Yield

e^{- D_{0} A}

e^{- D_{0} A /4}

ho jaati hai; ratio

e^{3 D_{0} A /4}

hai, jo depend karta hai ki original yield kitni buri thi, fixed factor of 4 nahi.

3D mein stack kiye gaye do chiplets ki total latency hamesha 2.5D mein side-by-side rakhne se kam hoti hai.

Generally False. 3D mein wires shorter hain isliye link latency kam hoti hai, lekin thermal throttling lower clocks force kar sakta hai, aur TSV routing apna overhead add karta hai — "shorter wire" poori latency story nahi hai.

Ek monolithic die aur same total area ke 4-chiplet version exactly utne hi defective transistors use se hatate hain.

False. Chiplet case mein defect sirf apna chhota die marta hai (jise tum discard karte ho); monolith mein ek defect poore bade die ko condemn kar deta hai. Same defects, waste hone wale good silicon ki matra bahut alag.

UCIe ek physical connector hai jise plug aur unplug kar sakte hain.

False. UCIe (Universal Chiplet Interconnect Express) ek die-to-die standard hai — ek protocol plus physical-layer spec — jo alag vendors ke chiplets ko interoperate karne deta hai; yeh dies mein fabricate hota hai, koi socket nahi hai.

Interconnect energy per bit voltage par wire length se zyada sharply depend karta hai.

True per the model.

E_{bit} = \frac{1}{2} C V^{2}

V

mein quadratic hai lekin

L

mein sirf linear (

C \propto L

ke through); voltage half karne par energy ~4× cut hoti hai, length half karne par sirf ~2×.

Reticle limit se neeche, monolithic jaana impossible hai.

False — bilkul ulta hai. Reticle limit (~858 mm²) woh maximum hai jo ek exposure pattern kar sakta hai; iske neeche monolithic bilkul possible hai aur chhote, high-yield dies ke liye often sasta choice hota hai.

Error dhundho

"200 mm² area aur

D_{0} = 0.005

wale chiplet ki yield

e^{- 0.005} \approx 0.995

hai."

Error yeh hai ki

D_{0}

ko area se multiply karna bhool gaye: yield hai

e^{- D_{0} A} = e^{- 0.005 \times 200} = e^{- 1} \approx 0.368

e^{- 0.005}

nahi.

"Chiplets hame process nodes mix karne dete hain kyunki interposer ek node ke signals ko doosre ke signals mein convert karta hai."

Interposer koi conversion nahi karta — yeh passive wiring hai. Nodes mix karna isliye kaam karta hai kyunki har die alag manufacture hoti hai, isliye har ek jo node suit kare woh choose kar sakti hai (dekho Heterogeneous integration).

"3D stacking better hai kyunki TSVs kisi bhi 2.5D wire se zyada bandwidth dete hain."

TSVs short vertical links dete hain, isliye 3D high bandwidth hit kar sakta hai — lekin asli driver proximity hai (short

L

), aur 2.5D bhi high-bandwidth ho sakta hai; claim TSVs ko sole cause ke roop mein overstate karta hai aur heat ko ignore karta hai.

"Yield

Y = e^{- D_{0} A}

at most ek defect ki probability count karta hai, kyunki chips kuch tolerate kar sakti hain."

Galat: yeh exactly zero defects ki probability hai. Model die ko good tab consider karta hai iff koi defect us par nahi landa; defects tolerate karna (redundancy ke zariye) ek alag, zyada optimistic model hai.

"Kyunki

C \propto L

hai, ek off-package PCB trace (cm) aur ek on-package link (µm) mein roughly same energy per bit lagti hai."

Bilkul ulta. Kyunki

E_{bit} \propto L

hai aur cm, µm se ~10⁴× lamba hai, off-package links orders of magnitude zyada energy per bit cost karte hain — yehi core reason hai dies ko paas laane ka (dekho Interconnect energy and dark silicon).

"Silicon bridges (jaise EMIB) full interposers se saste hain kyunki woh wiring ki jagah TSVs use karte hain."

Ulta hai. Bridge sasta isliye hai kyunki yeh ek chhoti silicon chip hai jo sirf do dies ke edges wire karti hai — tum ek bade interposer se bhi bachte ho aur mostly TSVs se bhi, unhe embrace nahi karte.

Why questions

Defects ke liye Poisson distribution kyun — bell curve kyun nahi — sahi model hai?

Kyunki defects rare, independent, spatially uniform events per unit area hain, jo exactly woh tile-limit setup hai jo

e^{- D_{0} A}

produce karta hai; Gaussian galat tarike se mean count ke around symmetric spread assume kar lega.

Energy model

V

ki jagah

V^{2}

kyun use karta hai?

Capacitor ko voltage

V

tak charge karne mein energy

\frac{1}{2} C V^{2}

store hoti hai; deliver ki gayi charge aur jis voltage ke against push hoti hai — dono

V

ke saath badhte hain, isliye energy

V \times V

scale karti hai, linearly nahi.

Wire capacitance length ke saath linearly kyun badhti hai?

Wire identical per-segment capacitors ki chain hai jo parallel-add hoti hain; length double karne par segment count double hota hai aur isliye

C

bhi, isliye

C \propto L

Chhoti die ke liye chiplets monolith se zyada expensive kyun ho sakte hain?

Chhoti die ki pehle se hi high monolithic yield hoti hai, isliye use split karne se almost kuch nahi bachta — phir bhi tum full packaging, assembly, test, aur duplicated die-to-die I/O overhead pay karte ho, jo ab dominate karta hai.

3D stacking mein heat manage karna 2.5D se zyada mushkil kyun hai?

Stacked dies directly ek doosre par baithe hain, isliye unki heat neighbouring silicon se guzar kar jaani chahiye; power density (W/mm²) badhti hai aur buried die heatsink tak easily nahi pahunch sakta, unlike side-by-side dies jinke paas apna top surface hota hai.

Industry logic-on-logic ki jagah logic-on-cache ko 3D ke liye kyun prefer karta hai?

Cache (SRAM) comparatively low-power hota hai, isliye ise hot logic par stack karna thoda heat add karta hai; do hot logic dies stacked karene par power density compound hogi aur aggressive throttling force ho sakti hai.

Computation ko chiplets mein move karna Moore's Law ke slowdown se kyun connect hota hai?

Jab ek single node cheaply transistors shrink aur reticle monolithic size cap kar de, tab bahut saare good chhote dies ko package karna practically system-level transistor count ko scale karte rehne ka tarika ban jaata hai.

Edge cases

Yield model kya predict karta hai jab die area

A \to \infty

Y = e^{- D_{0} A} \to 0

: infinitely bada die certainly ek defect pakdega, isliye yield vanish ho jaati hai — model sahi dikhata hai ki monolithic scaling collapse hoti hai (curve ko figure s02 mein floor par girte dekho).

Agar defect density

D_{0} = 0

ho (perfect process) toh yield ka kya hoga?

Y = e^{0} = 1

kisi bhi area ke liye — zero defects ke saath, size ka koi matter nahi (figure s02 mein flat dashed line) aur poora chiplet-vs-monolith yield argument disappear ho jaata hai; sirf reticle aur node-mixing ke reasons bachte hain.

Agar

N \to \infty

chiplets mein split karo, kya yield hamesha ke liye improve hoti rehti hai?

Per-chiplet yield

e^{- D_{0} A / N} \to 1

, lekin tumhe sabhi $N$ correctly assemble bhi karne hain; assembly-failure aur per-die I/O overhead

N

ke saath badhte hain, isliye total system yield aur cost eventually kharaab ho jaate hain. Ek optimum

N

hota hai, infinity nahi.

Reticle limit (~858 mm²) par exact die ke liye, chiplet splitting mandatory hai?

Mandatory nahi — tum ise abhi bhi monolithically print kar sakte ho ek exposure ki bilkul edge par; splitting tab hi forced hoti hai jab design limit exceed kare aur imperfect stitching ki zarurat ho (dekho Wafer yield and defect density ki wajah jaanne ke liye tum split kyun chahoge).

Agar do chiplets ko almost koi data exchange nahi karna hai, kya unhe physically paas laana phir bhi help karta hai?

Barely —

E_{bit} \propto L

ki saving sirf tab matter karti hai jab links heavily use hon. Kam traffic ke saath, cheap door-door placement (ya alag packages bhi) better trade ho sakti hai.

Recall Traps ka ek-sentence recap

Yield area mein exponential hai (linear nahi), energy win voltage mein quadratic, length mein linear hai, chiplets ek packaging tax pay karte hain jo sirf large ya node-mixed designs earn back karte hain, aur 3D ke short wires ke saath trapped heat bhi aati hai.

Connections

Wafer yield and defect density
Advanced packaging (2.5D 3D interposers)
Interconnect energy and dark silicon
Memory bandwidth and HBM
Heterogeneous integration
Moore's Law and its slowdown