Exercises — Chiplets and multi-die integration

The model is $Y=e^{-D_{0}A}.$ What it says: yield equals $e$ raised to minus the expected number of defects on the die. The assumption: defects are rare, independent, and uniformly (randomly) scattered — a Poisson process — and a die is good if and only if zero defects land on it. With $k$ = the number of defects on the die, setting $k=0$ in the Poisson formula $P(k)=\frac{(D_{0}A{)}^k{e}^{-D_{0}A}}{k!}$ gives $P(0)=e^{-D_{0}A}$ because $(D_{0}A{)}^0=1$ and $0!=1$.

The exponent is the expected defect count $D_{0}A=0.01\times 100=1$. $Y=e^{-1}\approx \mathrm{0.368.}$ So about 36.8% of these dies are good.

Monolithic: exponent $=0.005\times 600=3$, so $Y_{\text{mono}}=e^{-3}\approx 0.0498(\approx 5.0\%).$ Per chiplet: each chiplet has area $A/N=600/3=200$ mm², exponent $=0.005\times 200=1$: $Y_{\text{chiplet}}=e^{-1}\approx 0.368(\approx 36.8\%).$ Each small die is roughly $0.368/0.0498\approx 7.4\times$ more likely to be good than the monolith.

Voltage is equal and $\frac{1}{2}{V}^2$ is common, so energy scales purely with $C$, which scales with length $L$: $\frac{E_A}{E_B}=\frac{L_A}{L_B}=\frac{2000}{500}=4.$ The longer link burns 4× the energy per bit. This is exactly why we drag dies close together on an interposer instead of routing off-package.

Because we pre-test and discard bad chiplets, the silicon going into assembly is guaranteed good — the only remaining risk is the assembly step. So: $Y_{\text{package}}=Y_{\text{asm}}=\mathrm{0.95.}$ Contrast with monolithic $Y_{\text{mono}}=e^{-3}\approx 0.0498$. Reading it: known-good-die testing decouples silicon yield from the final product. We throw away roughly $63\%$ of chiplets at test (since only $36.8\%$ pass), but we never pay to package the doomed ones — and the finished-package yield jumps from $5\%$ to $95\%$.

Edge case — spare requirement (the hidden silicon cost). The "$Y_{\text{package}}=0.95$" answer quietly assumes we have $3$ good chiplets available. Getting one good chiplet needs, on average, $1/Y_{\text{chiplet}}=1/e^{-1}=e\approx 2.718$ raw chiplets fabricated. To assemble one package we need $3$ good ones, so the fab must produce on average: $3\times \frac{1}{Y_{\text{chiplet}}}=3e\approx 8.15\text{ raw chiplets per package.}$ What this means: the $95\%$ final yield is real, but it does not make the discarded silicon free — we still fab and scrap roughly $8.15-3=5.15$ chiplets' worth of silicon per package. The win is that we scrap small, cheap, untested dies instead of packaging large, doomed ones. The decoupling is between cost location (silicon vs package), not a free lunch.

Without testing, the events are independent, so multiply: $Y=\underset{\text{all 3 dies good}}{\underbrace{(e^{-1}{)}^3}}\times \underset{\text{assembly}}{\underbrace{0.95}}=e^{-3}\times 0.95\approx 0.0498\times 0.95\approx \mathrm{0.0473.}$ This is worse than the monolith ($e^{-3}\approx 0.0498$) because we added assembly risk on top of the same total silicon risk and gained nothing. Lesson: splitting into chiplets only pays off because we test each die first (known-good die). Blind assembly of untested chiplets is strictly worse than monolithic.

First, the break-even exponent (the actual question). Per unit of fabbed area — that is, per mm² of silicon we pattern on the wafer, whether it ends up good or scrapped — monolithic keeps a fraction $e^{-D_{0}A}$; chiplets keep $e^{-D_{0}A/N}$. Chiplets recover more good silicon when $e^{-D_{0}A/N}>e^{-D_{0}A}⟺-\frac{D_{0}A}{N}>-D_{0}A⟺D_{0}A\left(1-\frac{1}{N}\right)>0.$ Since $1-1/N>0$ for any $N\ge 2$, the inequality holds for every $D_{0}A>0$. The break-even exponent is therefore $D_{0}A=0$: at any positive defect exponent chiplets already recover more good silicon, and the advantage grows as the exponent grows. So there is no positive threshold to "cross" — the crossover sits at the degenerate point $D_{0}A=0$ (a perfect wafer, where both options are equal at $Y=1$).

Now the numeric yields for this product ($D_{0}A=3.2$, well above the $0$ break-even): Monolithic yield: exponent $=0.004\times 800=3.2$: $Y_{\text{mono}}=e^{-3.2}\approx 0.0408(4.08\%).$ Per-chiplet yield: $A/N=200$ mm², exponent $=0.004\times 200=0.8$: $Y_{\text{chiplet}}=e^{-0.8}\approx 0.4493(44.93\%).$ Good-silicon comparison per unit fabbed area: monolithic keeps a fraction $0.0408$ of its area; chiplets keep $0.4493$. Ratio: $\frac{0.4493}{0.0408}\approx \mathrm{11.0.}$ Splitting recovers roughly 11× more usable silicon per wafer.

Where $c$ and $P$ enter. The break-even above is purely about silicon recovered; the true economic decision weighs money. Chiplets are cheaper when the value of the recovered silicon exceeds the packaging overhead, i.e. roughly when $c\cdot (\text{extra good area recovered})>P.$ Here $c$ (dollars per good mm²) turns the $11\times$ silicon gain into dollars, and $P$ (fixed dollars per package for interposer/TSV/assembly/test) is the fee we must beat. Large $D_{0}A$ makes the left side big (huge recovery); a small, cheap die makes it small — and then $P$ wins and you stay monolithic. This is exactly the L5 economic break-even.

Energy (favours 3D): stacked dies use short vertical TSV links (tens of µm) versus 2.5D lateral links (hundreds–thousands of µm). Since $E_{\text{bit}}\propto L$, a $50\mu \text{m}$ TSV path versus a $2000\mu \text{m}$ lateral path is a $2000/50=40\times$ energy saving per bit — decisive for HBM-style stacks. Thermal (favours 2.5D): stacking multiplies power density (W/mm²) because two heat-producing dies share one footprint and the bottom die's heat must escape through the top. Four hot logic dies stacked would overheat. Verdict: use 3D for logic-on-cache (cache is low-power, thermally friendly) and 2.5D for four equally hot logic dies where you need to spread the heat over more area.

Setup. Per unit of fabbed area (mm² patterned on the wafer, good or scrapped), a monolithic die keeps a fraction $Y_{\text{mono}}=e^{-D_{0}A}$. Chiplets keep $Y_{\text{chiplet}}=e^{-D_{0}A/N}$ per unit fabbed area (each good chiplet is kept). The good-area multiplier is: $M(A)=\frac{Y_{\text{chiplet}}}{Y_{\text{mono}}}=\frac{e^{-D_{0}A/N}}{e^{-D_{0}A}}=e^{D_{0}A(1-1/N)}.$ Solve for the break-even $A^{\ast }$. Chiplets recover more good silicon exactly when $M(A)>1$, i.e. $e^{D_{0}A(1-1/N)}>1⟺D_{0}A\left(1-\frac{1}{N}\right)>0.$ Solving for the boundary $M(A)=1$ gives $D_0{A}^{\ast }(1-1/N)=0$. Since $D_0>0$ and $(1-1/N)>0$ for $N\ge 2$, the only solution is $A^{\ast }=0.$ Interpretation. The break-even area is $A^{\ast }=0$: for every positive die area, $M(A)>1$, so splitting never loses good silicon and the gain grows exponentially with area. There is no finite positive break-even for silicon recovery; the true (positive) break-even is economic — set by packaging cost $P$, treated in Problem 5.2 — not by silicon yield. Numeric, $N=2$, $D_{0}A=4$: $M=e^{4(1-1/2)}=e^2\approx \mathrm{7.389.}$ Splitting a $D_{0}A=4$ die in half recovers about 7.4× the good silicon — a large win, and this is precisely why chiplets shine on the biggest, most defect-exposed designs.

The arithmetic is right: $M(0.1)=e^{0.05}\approx 1.051$, a genuine ~5% silicon recovery. But recovered silicon is not the only cost. Splitting adds:

• Packaging overhead $P$ (interposer/bridge, TSVs, assembly, extra test) — a fixed cost that dwarfs a $5\%$ silicon saving on an already-cheap small die.
• Duplicated die-to-die I/O — each chiplet needs UCIe-style PHY area and power that a monolith spends once. At $D_{0}A=0.1$ the monolithic yield is already $e^{-0.1}\approx 90.5\%$ — great. A $5\%$ silicon gain cannot pay for a whole package. Conclusion: chiplets win when the monolithic area is large (yield already poor) or when you need to mix process nodes / reuse dies — not merely because $M>1$, which is always true. The claim confuses "recovers some silicon" with "cheaper overall".

Why does cutting a die into $N$ pieces and requiring all good give back the same $e^{-D_{0}A}$? ::: Because $(e^{-D_{0}A/N}{)}^N=e^{-D_{0}A}$ — the win only appears when you test and discard bad chiplets before assembly (known-good die).