Chiplets and multi-die integration: Exercises — Hinglish deep dive

6.5.1 · D4 · Hardware › Advanced & Emerging Architectures › Chiplets and multi-die integration

Definition Is page par har symbol, simple shabdon mein

$D_{0}$ = defect density = manufacturing defects ka average number per square millimetre of silicon. Socho ek wafer par random dust specks bikri hain; $D_{0}$ hai "specks per mm²".
$A$ = die area mm² mein — ek chip ka flat rectangular footprint.
$k$ = defects ki actual number jo ek particular die par girti hain — ek poora number $0, 1, 2, \dots$ Hum sabse zyada $k = 0$ ki parwah karte hain (ek bilkul saaf die).
$Y$ = yield = un dies ka fraction jo achhe nikle (unpar zero defects). $0$ aur $1$ ke beech ka ek pure number; percent mein padhne ke liye $100$ se multiply karo.
$N$ = chiplets ki number, jismein hum ek badi design ko kaatte hain.
$e$ = fixed number $2.71828 \dots$ Jab bhi koi quantity apne baaki hisse ke proportion mein khatam hoti hai, aapko $e^{- something}$ milta hai. Yahan woh "something" hai $D_{0} A$ : die par defects ka expected count.
$E_{bit}$ = ==ek wire par ek bit bhejna mein lagi energy==. $C$ = wire ki capacitance (usse kitna charge bharni padti hai), $V$ = voltage swing, $L$ = wire length. Law $E_{bit} = \frac{1}{2} C V^{2}$ mein $C \propto L$ ka matlab hai longer wire proportionally zyada energy per bit leta hai.
$c$ = raw silicon ka cost per unit good die-area (dollars per good mm²) — sirf L4 mein use hota hai.
$P$ = finished package per fixed packaging overhead (dollars: interposer, TSVs, assembly, extra test) — sirf L4 mein use hota hai.

Figure — Chiplets and multi-die integration

Picture poori intuition hai: exponent $D_{0} A$ literally shaded rectangle ki area hai — density times area = expected defect count. $A$ badhao aur exponent badhta hai, toh $Y = e^{- D_{0} A}$ curve par tezi se neeche slide karta hai.

L1 — Recognition

Problem 1.1 (L1)

Poisson yield model state karo aur woh ek assumption batao jisse hum ise likh sakte hain.

Recall Solution 1.1

Model hai $Y = e^{- D_{0} A} .$ Yeh kya kehta hai: yield barabar hai $e$ raised to minus die par expected number of defects. Assumption: defects rare, independent, aur uniformly (randomly) scattered hain — ek Poisson process — aur die achha hai agar aur sirf agar zero defects us par giren. $k$ = die par defects ki number ke saath, Poisson formula $P (k) = \frac{( D _{0} A ) ^{k} e ^{- D_{0} A}}{k !}$ mein $k = 0$ set karne se $P (0) = e^{- D_{0} A}$ milta hai kyunki $(D_{0} A)^{0} = 1$ aur $0! = 1$ .

Problem 1.2 (L1)

Ek die mein $D_{0} = 0.01$ defects/mm² aur $A = 100$ mm² hai. Uski yield compute karo.

Recall Solution 1.2

Exponent hai expected defect count $D_{0} A = 0.01 \times 100 = 1$ . $Y = e^{- 1} \approx 0.368.$ Toh lagbhag 36.8% dies achhi hain.

L2 — Application

Problem 2.1 (L2)

Wohi wafer, $D_{0} = 0.005$ defects/mm². Ek monolithic design ko $A = 600$ mm² chahiye. Monolithic yield compute karo, phir per-chiplet yield agar hum ise $N = 3$ equal chiplets mein split karein.

Recall Solution 2.1

Monolithic: exponent $= 0.005 \times 600 = 3$ , toh $Y_{mono} = e^{- 3} \approx 0.0498 (\approx 5.0%) .$ Per chiplet: har chiplet ki area $A / N = 600/3 = 200$ mm², exponent $= 0.005 \times 200 = 1$ : $Y_{chiplet} = e^{- 1} \approx 0.368 (\approx 36.8%) .$ Har chhota die monolith se roughly $0.368/0.0498 \approx 7.4 \times$ zyada likely achha nikalta hai.

Problem 2.2 (L2)

Do die-to-die links same voltage carry karte hain. Link A $2000 μ m$ lamba hai, link B $500 μ m$ lamba hai. $E_{bit} = \frac{1}{2} C V^{2}$ use karte hue $C \propto L$ ke saath, $E_{A} / E_{B}$ ka ratio kya hai?

Recall Solution 2.2

Voltage equal hai aur $\frac{1}{2} V^{2}$ common hai, toh energy purely $C$ ke saath scale karti hai, jo length $L$ ke saath scale karti hai: $\frac{E _{A}}{E _{B}} = \frac{L _{A}}{L _{B}} = \frac{2000}{500} = 4.$ Longer link 4× energy per bit jalata hai. Isliye hum dies ko interposer par paas paas laate hain instead of off-package route karne ke.

L3 — Analysis

Problem 3.1 (L3)

Problem 2.1 se, hamare paas $3$ chiplets hain har ek ki yield $e^{- 1} \approx 0.368$ hai. Maan lo chiplets pehle test hote hain (sirf known-good dies assemble hote hain) aur assembly step khud probability $Y_{asm} = 0.95$ se succeed karta hai. Finished package ke kaam karne ki probability kya hai? Monolithic $e^{- 3}$ se compare karo. Phir, edge case ke roop mein: average mein kitne raw chiplets fab ko produce karne padte hain per finished package taaki haath mein hamesha $3$ known-good dies ho?

Recall Solution 3.1

Kyunki hum pre-test karte hain aur kharab chiplets discard karte hain, assembly mein jaane wala silicon guaranteed achha hai — bacha hua risk sirf assembly step hai. Toh: $Y_{package} = Y_{asm} = 0.95.$ Monolithic $Y_{mono} = e^{- 3} \approx 0.0498$ se compare karo. Padho: known-good-die testing silicon yield ko final product se decouple karta hai. Assembly mein roughly $63%$ chiplets throw away ho jaate hain test par (kyunki sirf $36.8%$ pass hote hain), lekin hum doomed walo ko package karne ke liye kabhi nahi dete — aur finished-package yield $5%$ se $95%$ tak jump kar jaati hai.

Edge case — spare requirement (hidden silicon cost). " $Y_{package} = 0.95$ " answer quietly assume karta hai ki hamare paas $3$ achhe chiplets hain. Ek achha chiplet milne ke liye average mein $1/ Y_{chiplet} = 1/ e^{- 1} = e \approx 2.718$ raw chiplets fabricate karne padte hain. Ek package assemble karne ke liye $3$ achhe chahiye, isliye fab ko average mein produce karna padega: $3 \times \frac{1}{Y _{chiplet}} = 3 e \approx 8.15 raw chiplets per package.$ Iska matlab: $95%$ final yield real hai, lekin iska matlab discarded silicon free nahi hai — hum phir bhi per package roughly $8.15 - 3 = 5.15$ chiplets worth silicon fab aur scrap karte hain. Jeet yeh hai ki hum chhote, saste, untested dies scrap karte hain instead of bade, doomed ones package karne ke. Decoupling cost location (silicon vs package) ke beech hai, free lunch nahi.

Problem 3.2 (L3)

Ab maan lo humne pre-test nahi kiya — teeno chiplets blindly assemble ho jaate hain, aur package tab kaam karta hai jab teeno achhe aur assembly succeed hoti hai. Yeh yield compute karo aur explain karo ki pre-testing kyun zaroori hai.

Recall Solution 3.2

Bina testing ke, events independent hain, toh multiply karo: $Y = teeno dies achhe (e^{- 1})^{3} \times assembly 0.95 = e^{- 3} \times 0.95 \approx 0.0498 \times 0.95 \approx 0.0473.$ Yeh monolith ( $e^{- 3} \approx 0.0498$ ) se bura hai kyunki humne usi total silicon risk ke upar assembly risk add kar di aur kuch gain nahi kiya. Lesson: chiplets mein split karna tabhi fayda deta hai jab hum pehle har die test karte hain (known-good die). Untested chiplets ki blind assembly monolithic se strictly kharab hai.

L4 — Synthesis

Problem 4.1 (L4)

Ek product ko $A = 800$ mm² logic chahiye. Wafer: $D_{0} = 0.004$ defects/mm². Raw silicon ka cost $\$ c $p er g oo d m m^{2} d i e - a r e ahai, a u r c hi pl e tp r o d u c tp a c k a g e k a r n e m e in e k f i x e d o v er h e a d$ $P $p er p a c k a g e a dd h o t ahai . A sse mb l y f ai l u r es i g n or e k a r t e h u e, k i s d e f ec t e x p o n e n tp a r$ N=4 $c hi pl e t s m e in s pl i t k a r nam o n o l i t hi csez y a d a g oo d s i l i co n p er w a f er r eco v er k a r t ahai ? N u m er i cy i e l d s d o, p hi r ba t a o k i$ c $a u r$ P$ economic decision mein kahan aate hain.

Recall Solution 4.1

Pehle, break-even exponent (actual question). Per unit fabbed area — matlab, per mm² silicon jo hum wafer par pattern karte hain, chahe woh achha nikle ya scrap ho — monolithic ek fraction $e^{- D_{0} A}$ rakhta hai; chiplets $e^{- D_{0} A / N}$ per unit fabbed area rakhte hain (har achha chiplet rakha jaata hai). Chiplets zyada achha silicon recover karte hain jab $e^{- D_{0} A / N} > e^{- D_{0} A} ⟺ - \frac{D _{0} A}{N} > - D_{0} A ⟺ D_{0} A (1 - \frac{1}{N}) > 0.$ Kyunki $1 - 1/ N > 0$ kisi bhi $N \geq 2$ ke liye, inequality har $D_{0} A > 0$ ke liye hold karti hai. Break-even exponent isliye $D_{0} A = 0$ hai: kisi bhi positive defect exponent par chiplets pehle se zyada good silicon recover karte hain, aur advantage exponent ke badhne ke saath badhta hai. Toh "cross" karne ke liye koi positive threshold nahi hai — crossover degenerate point $D_{0} A = 0$ par baitha hai (ek perfect wafer, jahan dono options $Y = 1$ par equal hain).

Ab is product ke liye numeric yields ( $D_{0} A = 3.2$ , $0$ break-even se kaafi upar): Monolithic yield: exponent $= 0.004 \times 800 = 3.2$ : $Y_{mono} = e^{- 3.2} \approx 0.0408 (4.08%) .$ Per-chiplet yield: $A / N = 200$ mm², exponent $= 0.004 \times 200 = 0.8$ : $Y_{chiplet} = e^{- 0.8} \approx 0.4493 (44.93%) .$ Per unit fabbed area good-silicon comparison: monolithic apni area ka fraction $0.0408$ rakhta hai; chiplets $0.4493$ rakhte hain. Ratio: $\frac{0.4493}{0.0408} \approx 11.0.$ Split karne se roughly 11× zyada usable silicon per wafer recover hota hai.

$c$ aur $P$ kahan aate hain. Upar ka break-even purely recovered silicon ke baare mein hai; asli economic decision paise weighs karta hai. Chiplets saste hain jab recovered silicon ki value packaging overhead se zyada ho, matlab roughly jab $c \cdot (extra good area recovered) > P .$ Yahan $c$ (dollars per good mm²) $11 \times$ silicon gain ko dollars mein convert karta hai, aur $P$ (fixed dollars per package interposer/TSV/assembly/test ke liye) woh fee hai jise humein beat karna hai. Bada $D_{0} A$ left side bada karta hai (huge recovery); ek chhota, sasta die ise chota karta hai — aur phir $P$ jeet jaata hai aur aap monolithic rehte ho. Yahi L5 economic break-even hai.

Problem 4.2 (L4)

Usi product ke liye, aap $4$ chiplets ko 2.5D (side-by-side on an interposer) mein kab route karoge versus 3D (stacked) mein? Apna answer ek quantitative link-energy fact aur ek thermal fact se jodo.

Recall Solution 4.2

Energy (3D favour karta hai): stacked dies short vertical TSV links use karte hain (tens of µm) versus 2.5D lateral links (hundreds–thousands of µm). Kyunki $E_{bit} \propto L$ , ek $50 μ m$ TSV path versus ek $2000 μ m$ lateral path $2000/50 = 40 \times$ energy saving per bit hai — HBM-style stacks ke liye decisive. Thermal (2.5D favour karta hai): stacking power density (W/mm²) multiply karta hai kyunki do heat-producing dies ek footprint share karte hain aur bottom die ki heat through top se escape karni padti hai. Char hot logic dies stacked overheat kar jaate. Verdict: 3D use karo logic-on-cache ke liye (cache low-power, thermally friendly hai) aur 2.5D char equally hot logic dies ke liye jahan aapko heat zyada area par spread karni ho.

L5 — Mastery

Problem 5.1 (L5)

General break-even area $A^{*}$ derive karo jiske upar ek monolithic die ko $N$ equal chiplets mein split karna per wafer zyada total good area yield karta hai, yeh assume karte hue ki pre-testing har achhe chiplet ko rakhta hai. Phir $N = 2$ ke liye $D_{0} A = 4$ par good-area multiplier $M (A)$ evaluate karo.

Recall Solution 5.1

Setup. Per unit fabbed area (mm² wafer par patterned, good ya scrapped) ke, ek monolithic die ek fraction $Y_{mono} = e^{- D_{0} A}$ rakhta hai. Chiplets $Y_{chiplet} = e^{- D_{0} A / N}$ per unit fabbed area rakhte hain (har achha chiplet rakha jaata hai). Good-area multiplier hai: $M (A) = \frac{Y _{chiplet}}{Y _{mono}} = \frac{e ^{- D_{0} A / N}}{e ^{- D_{0} A}} = e^{D_{0} A (1 - 1/ N)} .$ Break-even $A^{*}$ solve karo. Chiplets zyada good silicon tab recover karte hain jab $M (A) > 1$ , matlab $e^{D_{0} A (1 - 1/ N)} > 1 ⟺ D_{0} A (1 - \frac{1}{N}) > 0.$ Boundary $M (A) = 1$ ke liye solve karne par $D_{0} A^{*} (1 - 1/ N) = 0$ milta hai. Kyunki $D_{0} > 0$ aur $(1 - 1/ N) > 0$ for $N \geq 2$ , ek hi solution hai $A^{*} = 0.$ Interpretation. Break-even area $A^{*} = 0$ hai: har positive die area ke liye, $M (A) > 1$ , toh splitting kabhi good silicon nahi gawaata aur gain area ke saath exponentially badhta hai. Silicon recovery ke liye koi finite positive break-even nahi hai; asli (positive) break-even economic hai — packaging cost $P$ se set hota hai, Problem 5.2 mein treat kiya — silicon yield se nahi. Numeric, $N = 2$ , $D_{0} A = 4$ : $M = e^{4 (1 - 1/2)} = e^{2} \approx 7.389.$ $D_{0} A = 4$ die ko aadha karne se roughly 7.4× good silicon recover hota hai — ek bada win, aur yahi precisely hai kyun chiplets sabse bade, sabse zyada defect-exposed designs par shine karte hain.

Problem 5.2 (L5)

Ek designer claim karta hai: "Ek tiny $D_{0} A = 0.1$ die ke liye, chiplets phir bhi $M = e^{0.1 (1 - 1/2)} = e^{0.05} \approx 1.05$ recover karte hain — $5%$ silicon gain, toh hamesha split karna chahiye." Is claim ki critique karo parent note ke trade-offs use karke.

Recall Solution 5.2

Arithmetic sahi hai: $M (0.1) = e^{0.05} \approx 1.051$ , ek genuine ~5% silicon recovery. Lekin recovered silicon ek hi cost nahi hai. Splitting add karta hai:

Packaging overhead $P$ (interposer/bridge, TSVs, assembly, extra test) — ek fixed cost jo ek already-cheap chhote die par $5%$ silicon saving se kaafi zyada hai.
Duplicated die-to-die I/O — har chiplet ko UCIe-style PHY area aur power chahiye jo ek monolith ek baar spend karta hai. $D_{0} A = 0.1$ par monolithic yield pehle se $e^{- 0.1} \approx 90.5%$ hai — great. $5%$ silicon gain poore package ke liye pay nahi kar sakta. Conclusion: chiplets tab jeetat hain jab monolithic area bada ho (yield pehle se kharab) ya jab aapko process nodes mix karni hoin / dies reuse karni hoin — sirf isliye nahi ki $M > 1$ , jo hamesha sach hai. Claim "kuch silicon recover karta hai" aur "overall sasta" mein confusion karta hai.

Recall Jaane se pehle ek-line self-test

Ek die ko $N$ pieces mein kaatna aur sab achhe hone ki requirement wahi $e^{- D_{0} A}$ wapas kyun deta hai? ::: Kyunki $(e^{- D_{0} A / N})^{N} = e^{- D_{0} A}$ — win tab hi aata hai jab aap fabrication aur assembly ke beech kharab chiplets test aur discard karte ho (known-good die).

Connections

Chiplets and multi-die integration (parent)
Wafer yield and defect density — $Y = e^{- D_{0} A}$ ka source
Interconnect energy and dark silicon — $E_{bit} \propto L$ ka source
Advanced packaging (2.5D 3D interposers) — L4 ke peeche 2.5D/3D mechanics
Memory bandwidth and HBM — classic 3D-stack payoff
Heterogeneous integration — nodes mix karna, UCIe interfaces
Moore's Law and its slowdown — kyun yeh poori strategy aayi