Chiplets and multi-die integration — Hinglish notes

6.5.1 · Hardware › Advanced & Emerging Architectures

YEH exist kyun karta hai? (Woh problem jo solve ho rahi hai)

Derivation: yield bade dies ko saza kyun deti hai

Defects ko random points ki tarah model karo jo wafer par density $D_{0}$ (defects per mm²) ke saath bikre hue hain. Ek die tabhi survive karta hai jab zero defects uske upar land karein. Agar defects Poisson process follow karein, toh area $A$ par $k$ defects ki probability hai:

$P (k) = \frac{( D _{0} A ) ^{k} e ^{- D_{0} A}}{k !}$

Poisson kyun? Defects rare, independent, spatially uniform events hain — yahi exactly Poisson setup hai.

Yield = zero defects ki probability, yaani $k = 0$ :

$Y = P (0) = e^{- D_{0} A}$

Yeh step kyun? $k = 0$ plug karo: $(D_{0} A)^{0} = 1$ aur $0! = 1$ , sirf $e^{- D_{0} A}$ bachta hai.

Ab area $A$ ka ek bada die $N$ chiplets mein split karo jahan har ek ka area $A / N$ hai. Har chiplet ki yield hai:

$Y_{chiplet} = e^{- D_{0} A / N}$

Har chiplet individually zyada likely achha hoga. Hum test karte hain aur kharab waale phenk dete hain ("known-good die", KGD) assembly se pehle, isliye sirf achha silicon package karne mein paisa lagta hai.

CHIPLET precisely kya hai?

Key supporting terms:

Interposer — ek passive (ya active) slab (aksar silicon) jo unke upar rakhe dies ke beech dense wiring carry karta hai (2.5D).
Silicon bridge — ek chhota silicon chip jo substrate mein embedded hai aur do neighbouring dies ke edges ko connect karta hai (e.g. Intel EMIB) — full interposer se sasta.
TSV (Through-Silicon Via) — ek vertical copper via jo ek die ke through drill hota hai taaki signals top-to-bottom pass ho sakein (3D stacking ke liye zaroori).
Die-to-die (D2D) interface — woh protocol + physical layer jis par chiplets baat karte hain, e.g. UCIe standard (Universal Chiplet Interconnect Express).

Dies connect kaise hote hain? (2.5D vs 3D)

Figure — Chiplets and multi-die integration

Closeness bandwidth kyun deta hai?

Bandwidth per unit area scale hoti hai kitni wires pack kar sakte ho, aur short wires kam energy se fast chal sakti hain. Interconnect energy roughly distance ke saath scale hoti hai:

$E_{bit} \propto C \cdot V^{2}, C \propto L$

Kyun? Ek wire ki capacitance $C$ uski length $L$ ke saath badhti hai; har bit pe ise charge karne mein $\frac{1}{2} C V^{2}$ lagta hai. Chhote die-to-die links (µm scale on-package) bahut kam energy per bit lete hain compared to off-package PCB trace (cm scale) ke.

Trade-offs (steel-manned)

Flashcards

Yield die area badhne se kyun girti hai?

Defects ~uniform random hote hain; yield

Y = e^{- D_{0} A}

area ke saath exponentially girta hai, isliye bade dies zyada defects pakad te hain.

Poisson yield model aur uska assumption batao.

Y = e^{- D_{0} A}

; assume karta hai ki defects rare, independent, uniformly distributed hain (Poisson process), aur die tab achha hai jab zero defects hon.

Chiplet kya hai?

Ek chhota, independently manufactured die jo system ka part implement karta hai, dusre dies ke saath ek package mein combine hota hai.

2.5D aur 3D integration mein kya fark hai?

2.5D = dies side-by-side neeche interposer/bridge ke through wired; 3D = dies vertically stacked TSVs ke through wired.

TSV kya hai aur kyun zaroori hai?

Through-Silicon Via — ek vertical conductor jo die ke through jaata hai signals ko top-to-bottom pass karne deta hai; 3D stacking ke liye zaroori hai.

UCIe kya hai?

Universal Chiplet Interconnect Express — ek standard die-to-die interface (protocol + physical layer) interoperable chiplets ke liye.

Chhoti die-to-die links energy kyun bachate hain?

E_{bi t} = \frac{1}{2} C V^{2}

aur

C \propto L

; chhoti wires mein kam capacitance hoti hai, isliye kam energy per bit.

Do reasons batao chiplets monolithic se kharab kyun ho sakte hain.

Added packaging/assembly/test cost, plus duplicated D2D I/O area & power — nuksandeh jab die chhoti ho (already high yield).

Reticle limit kya hai aur yeh kyun matter karta hai?

~858 mm² maximum area jo lithography ek exposure mein pattern kar sakti hai; is se bada monolithic die print nahi kar sakte.

3D stacking mein heat problem kyun hoti hai?

Stacked dies ek dusre ko heat karte hain, power density (W/mm²) badhti hai; bottom die ki heat top se pass karni padti hai, cooling limit ho jaati hai.

Chiplets economically kab jeetatein hain?

Jab monolithic area bada ho (poor yield), process nodes mix karne ki zaroorat ho, ya same die ko products mein reuse karna ho.

Recall Feynman: 12-saal ke bachche ko explain karo

Socho ek giant sheet par cookies bake kar rahe ho, lekin kabhi kabhi ek kismis (defect) randomly gir jaati hai. Agar aap ek bahut badi cookie bake karo, ek kismis poori cheez kharab kar deti hai — bahut wasteful. Agar aap bahut saari chhoti cookies bake karo, ek buri kismis sirf ek chhoti cookie kharab karti hai; woh phenk do aur baaki rakh lo. Chiplets wahi chhoti cookies hain: hum chhote chips bake karte hain, har ek ko taste-test karte hain, sirf achhe rakhte hain, phir unhe ek "super cookie" package mein glue kar dete hain. Unhe paas glue karna unhe fast baat karne deta hai bina energy waste kiye — lekin unhe ek dusre ke upar stack karne se woh garm ho jaate hain, jaise cookies ek dusre ko steam karti hain.

Connections

Wafer yield and defect density — woh $e^{- D_{0} A}$ math jo chiplets ko motivate karta hai.
Advanced packaging (2.5D 3D interposers) — dies glue karne ka "how".
Moore's Law and its slowdown — kyun dies split karna attractive bana.
Memory bandwidth and HBM — HBM 3D-stacked DRAM hai, ek chiplet success story.
Interconnect energy and dark silicon — $E_{bi t} = \frac{1}{2} C V^{2}$ closeness argument ko power deta hai.
Heterogeneous integration — process nodes ko per die mix karna.