Exercises — 3D stacking and through-silicon vias (TSV)

WHAT: identify the two liner rings around the copper.

• Ring 1 (inner) = oxide liner. Silicon is semiconducting; without this insulator the copper core would electrically short to the substrate. In the coax model this oxide is the dielectric of permittivity $\epsilon$ between core radius $a$ and outer radius $b$.
• Ring 2 = barrier (e.g. TaN). Copper atoms diffuse into silicon and poison the transistors (deep-level traps that ruin carrier lifetime). The barrier stops that diffusion.

Answer: core = copper; then oxide liner (stops the short), then barrier (stops Cu diffusion), then bulk Si. See Interconnect RC Delay for why we care about the oxide thickness electrically.

Answer: 2.5D integration. The dies are beside each other, not stacked. The TSVs live in the passive slab beneath them — the interposer — not through the compute dies themselves. Contrast: true 3D stacks dies directly on top of one another with TSVs passing through the active dies. See Interposers and 2.5D Integration.

Step 1 — WHAT/WHY: absolute permittivity of the oxide, because the coax formula needs $\epsilon$, not the relative number. $\epsilon ={\epsilon }_r{\epsilon }_0=3.9\times 8.85\times 10^{-12}=3.45\times 10^{-11}\text{F/m}.$ Step 2 — the geometry factor. The log $\ln (b/a)$ comes straight from integrating the radial field across the oxide (that's where the coax formula was born). $\ln (b/a)=\ln (1.8/1.5)=\ln (1.2)=\mathrm{0.1823.}$ Step 3 — assemble. $C=\frac{2\pi \epsilon h}{\ln (b/a)}=\frac{2\pi (3.45\times 10^{-11})(40\times 10^{-6})}{0.1823}=4.76\times 10^{-14}\text{F}\approx 48\text{fF}.$ Tens of femtofarads — exactly the real-world range.

WHY this formula: every time a wire flips 0→1 you charge its capacitance to $V$; the energy delivered that ends up dissipated is $\frac{1}{2}C{V}^2$. $E=\frac{1}{2}C{V}^2=\frac{1}{2}(4.76\times 10^{-14})(0.8{)}^2=1.52\times 10^{-14}\text{J}\approx 15\text{fJ}.$

WHY square, not linear: a wire is both a resistor ($R\propto \ell$) and a capacitor ($C\propto \ell$); delay tracks the product $RC\propto {\ell }^2$. Doubling length quadruples delay. $\frac{{\tau }_{3D}}{{\tau }_{2D}}={\left(\frac{h}{{\ell }_{2D}}\right)}^2={\left(\frac{45}{6000}\right)}^2=(7.5\times 10^{-3}{)}^2=5.6\times 10^{-5}.$ The vertical path is about $1/5.6\times 10^{-5}\approx 1.8\times 10^4$ — roughly 18,000× faster. This squared saving is the whole physical justification for enduring TSV manufacturing pain. See Interconnect RC Delay.

WHY these formulas: 2D chips talk only through the edge (a 1D perimeter → grows like $L$); TSVs use the whole face (a 2D area → grows like $L^2$). $N_{2D}=\frac{4L}{p}=\frac{4(12\times 10^3\mu m)}{45\mu m}=\frac{48000}{45}=1067.$ $N_{3D}=\frac{L^2}{p^2}={\left(\frac{12000}{45}\right)}^2=(266.7{)}^2=71,111.$ $\text{ratio}=\frac{N_{3D}}{N_{2D}}=\frac{71111}{1067}\approx \mathrm{66.7.}$ ~67× more parallel links. This area-scaling is precisely why High Bandwidth Memory (HBM) can run a 1024-bit-wide bus.

WHY: bandwidth = bus width × per-lane rate; divide by 8 to convert bits→bytes. $BW=1024\times 3.6\times 10^9\text{bit/s}=3.686\times 10^{12}\text{bit/s}.$ $=\frac{3.686\times 10^{12}}{8}=4.608\times 10^{11}\text{B/s}=461\text{GB/s per stack}.$ Several stacks → multiple TB/s, feasible only because TSVs give area-scaled I/O (Exercise 6).

(a) Same $E=\frac{1}{2}C{V}^2$ for both, only $C$ changes. $E_{2D}=\frac{1}{2}(1.1\times 10^{-12})(0.64)=3.52\times 10^{-13}\text{J}.$ $E_{3D}=\frac{1}{2}(4.76\times 10^{-14})(0.64)=1.52\times 10^{-14}\text{J}.$ (b) ratio $=E_{2D}/E_{3D}=3.52\times 10^{-13}/1.52\times 10^{-14}\approx 23$. About 23× less energy per bit (dominated by the $23\times$ smaller $C$, since $V$ cancels). (c) Power saved = (energy saved per bit) × (bit rate). $\Delta E=3.52\times 10^{-13}-1.52\times 10^{-14}=3.37\times 10^{-13}\text{J}.$ $P_{\text{saved}}=3.37\times 10^{-13}\times 2\times 10^{12}=0.674\text{W}.$ Two-thirds of a watt saved on just this one migrated data path — multiplied across a chip, it's the difference between fitting in a power budget or not.

WHY this law: heat needs a temperature gradient to flow; more thickness $t$ between hotspot and heatsink means a steeper drop, i.e. a hotter buried layer. $\Delta T_1=\frac{(5)(100\times 10^{-6})}{(150)(1\times 10^{-4})}=\frac{5\times 10^{-4}}{1.5\times 10^{-2}}=0.0333\text{K}.$ $\Delta T_4=\frac{(5)(400\times 10^{-6})}{(150)(1\times 10^{-4})}=0.1333\text{K}.$ Thicker stack ⇒ 4× larger $\Delta T$ for the same heat. (Small numbers per hotspot, but they add across many hotspots and much larger real $Q$.) The physical message: stacking layers deepens the thermal path — see Thermal Management in ICs.

WHAT: invert the coax formula for $b$. WHY: the only free lever here is oxide thickness ($b$), since $a,h,\epsilon$ are fixed. Start from $C=\frac{2\pi \epsilon h}{\ln (b/a)}$. Solve for the log: $\ln (b/a)=\frac{2\pi \epsilon h}{C}.$ With $\epsilon =3.45\times 10^{-11}$ F/m, $h=40\times 10^{-6}$ m, $C=35\times 10^{-15}$ F: $\ln (b/a)=\frac{2\pi (3.45\times 10^{-11})(40\times 10^{-6})}{35\times 10^{-15}}=\frac{8.67\times 10^{-15}}{35\times 10^{-15}}=\mathrm{0.2478.}$ $b=a{e}^{0.2478}=1.5\mu m\times 1.281=1.92\mu m.$ Answer: oxide must reach $b\gtrsim 1.92\mu m$ (liner thickness $b-a\approx 0.42\mu m$). Trade-off accepted: thicker oxide → larger overall TSV diameter → bigger keep-out zone stealing active silicon, and slower/harder to fill. You bought lower capacitance with area and manufacturability. Contrast with Chip Packaging constraints.

WHAT: find $N$ where cumulative savings equal the overhead. WHY: a shortcut that saves $\Delta E$ per use only wins once total savings exceed the one-time cost — classic break-even. Savings per bit-move: $\Delta E=E_{2D}-E_{3D}=3.52\times 10^{-13}-1.52\times 10^{-14}=3.37\times 10^{-13}$ J. Break-even: $N\Delta E=E_{\text{oh}}$ $N=\frac{E_{\text{oh}}}{\Delta E}=\frac{8\times 10^{-13}}{3.37\times 10^{-13}}\approx \mathrm{2.37.}$ Answer: just ~3 bit-moves pay it back — the per-bit saving so dwarfs this modelled overhead that break-even is essentially immediate for any real workload (billions of moves). The insight: for high-traffic paths 3D is almost always worth it energetically; the true limiter stays thermal, not payback (see Exercises 9–10).

Total power (drives $Q$, which drives $\Delta T$ via Exercise 9):

• Option A: $4\times 5=20$ W.
• Option B: $1\times 5+3\times 1=8$ W. Answer: Option B dissipates 8 W vs 20 W — a 12 W (2.5×) lower heat load in the same footprint, so it runs much cooler and needs less throttling. This is exactly why real 3D is memory-on-logic. Why cooler can be slower: Option A has 4× the raw compute; if you could cool it, it would out-compute B. But at 20 W in one footprint the buried logic dies overheat (Exercise 9's $\Delta T$ scales with both $Q$ and stack thickness $t$), forcing clock throttling that erases the compute advantage. Rescue for A: microfluidic (interlayer liquid) cooling — channels etched between dies remove heat from inside the stack instead of only top/bottom, decoupling power from the thermal wall. Also see Thermal Management in ICs and, for the historical driver of all this density pressure, Moore's Law.

Delay of a wire scales with its length as ==${\ell }^2$== because it is both an $R\propto \ell$ and a $C\propto \ell$. In the coax model, increasing oxide outer radius $b$ makes $C$ smaller (bigger $\ln (b/a)$ denominator). 2D I/O grows like the perimeter ($L$); TSV I/O grows like the area ($L^2$). The real ceiling on 3D logic stacking is heat / power density, not wire delay.