Exercises — 3D stacking and through-silicon vias (TSV)

WHAT: copper ke aas paas ki do liner rings ko identify karo.

• Ring 1 (inner) = oxide liner. Silicon semiconducting hota hai; is insulator ke bina copper core substrate se electrically short ho jaata. Coax model mein yahi oxide, core radius $a$ aur outer radius $b$ ke beech ka dielectric hai, jiska permittivity $\epsilon$ hai.
• Ring 2 = barrier (jaise TaN). Copper atoms silicon mein diffuse ho jaate hain aur transistors ko poison kar dete hain (deep-level traps jo carrier lifetime ko barbaad kar dete hain). Barrier us diffusion ko rokta hai.

Answer: core = copper; phir oxide liner (short rokta hai), phir barrier (Cu diffusion rokta hai), phir bulk Si. Dekho Interconnect RC Delay — kyun oxide thickness electrically matter karti hai.

Answer: 2.5D integration. Dies ek doosre ke upar nahi, balki saath mein hain. TSVs unke neeche ke passive slab mein hain — interposer — compute dies ke through nahi. Contrast karo: sachchi 3D stacking mein dies seedha ek doosre ke upar hoti hain aur TSVs active dies ke through jaate hain. Dekho Interposers and 2.5D Integration.

Step 1 — WHAT/WHY: oxide ki absolute permittivity, kyunki coax formula ko $\epsilon$ chahiye, relative number nahi. $\epsilon ={\epsilon }_r{\epsilon }_0=3.9\times 8.85\times 10^{-12}=3.45\times 10^{-11}\text{F/m}.$ Step 2 — geometry factor. Log $\ln (b/a)$ seedha oxide ke across radial field integrate karne se aata hai (yahi se coax formula janam leta hai). $\ln (b/a)=\ln (1.8/1.5)=\ln (1.2)=\mathrm{0.1823.}$ Step 3 — assemble karo. $C=\frac{2\pi \epsilon h}{\ln (b/a)}=\frac{2\pi (3.45\times 10^{-11})(40\times 10^{-6})}{0.1823}=4.76\times 10^{-14}\text{F}\approx 48\text{fF}.$ Tens of femtofarads — bilkul real-world range.

WHY yeh formula: jab bhi ek wire 0→1 flip hoti hai, uski capacitance $V$ tak charge hoti hai; jo energy deliver hoti hai aur dissipate hoti hai woh $\frac{1}{2}C{V}^2$ hai. $E=\frac{1}{2}C{V}^2=\frac{1}{2}(4.76\times 10^{-14})(0.8{)}^2=1.52\times 10^{-14}\text{J}\approx 15\text{fJ}.$

WHY square, linear nahi: ek wire dono ek resistor hai ($R\propto \ell$) aur ek capacitor ($C\propto \ell$); delay product $RC\propto {\ell }^2$ track karta hai. Length double karo toh delay chaar guna ho jaata hai. $\frac{{\tau }_{3D}}{{\tau }_{2D}}={\left(\frac{h}{{\ell }_{2D}}\right)}^2={\left(\frac{45}{6000}\right)}^2=(7.5\times 10^{-3}{)}^2=5.6\times 10^{-5}.$ Vertical path lagbhag $1/5.6\times 10^{-5}\approx 1.8\times 10^4$ — roughly 18,000× tez hai. Yeh squared saving hi TSV manufacturing pain sehne ki poori physical justification hai. Dekho Interconnect RC Delay.

WHY yeh formulas: 2D chips sirf edge ke through communicate karte hain (ek 1D perimeter → $L$ ki tarah badhta hai); TSVs poori face use karte hain (ek 2D area → $L^2$ ki tarah badhta hai). $N_{2D}=\frac{4L}{p}=\frac{4(12\times 10^3\mu m)}{45\mu m}=\frac{48000}{45}=1067.$ $N_{3D}=\frac{L^2}{p^2}={\left(\frac{12000}{45}\right)}^2=(266.7{)}^2=71,111.$ $\text{ratio}=\frac{N_{3D}}{N_{2D}}=\frac{71111}{1067}\approx \mathrm{66.7.}$ ~67× zyada parallel links. Yahi area-scaling ki wajah se High Bandwidth Memory (HBM) ek 1024-bit-wide bus run kar sakta hai.

WHY: bandwidth = bus width × per-lane rate; bits→bytes convert karne ke liye 8 se divide karo. $BW=1024\times 3.6\times 10^9\text{bit/s}=3.686\times 10^{12}\text{bit/s}.$ $=\frac{3.686\times 10^{12}}{8}=4.608\times 10^{11}\text{B/s}=461\text{GB/s per stack}.$ Kai stacks → multiple TB/s, yeh sirf isliye feasible hai kyunki TSVs area-scaled I/O dete hain (Exercise 6).

(a) Dono ke liye wohi $E=\frac{1}{2}C{V}^2$, sirf $C$ badlega. $E_{2D}=\frac{1}{2}(1.1\times 10^{-12})(0.64)=3.52\times 10^{-13}\text{J}.$ $E_{3D}=\frac{1}{2}(4.76\times 10^{-14})(0.64)=1.52\times 10^{-14}\text{J}.$ (b) ratio $=E_{2D}/E_{3D}=3.52\times 10^{-13}/1.52\times 10^{-14}\approx 23$. Lagbhag 23× kam energy per bit ($23\times$ chhote $C$ ki wajah se, kyunki $V$ cancel ho jaata hai). (c) Power saved = (energy saved per bit) × (bit rate). $\Delta E=3.52\times 10^{-13}-1.52\times 10^{-14}=3.37\times 10^{-13}\text{J}.$ $P_{\text{saved}}=3.37\times 10^{-13}\times 2\times 10^{12}=0.674\text{W}.$ Sirf ek migrated data path par do-third watt bachte hain — poore chip par multiply karo, toh yeh power budget mein fit hone aur na hone ka farq hai.

WHY yeh law: heat ko flow karne ke liye temperature gradient chahiye; hotspot aur heatsink ke beech zyada thickness $t$ matlab zyada steep drop, yaani zyada garam buried layer. $\Delta T_1=\frac{(5)(100\times 10^{-6})}{(150)(1\times 10^{-4})}=\frac{5\times 10^{-4}}{1.5\times 10^{-2}}=0.0333\text{K}.$ $\Delta T_4=\frac{(5)(400\times 10^{-6})}{(150)(1\times 10^{-4})}=0.1333\text{K}.$ Mota stack ⇒ same heat ke liye 4× bada $\Delta T$. (Numbers per hotspot chhote hain, lekin kai hotspots aur kaafi bade real $Q$ par add hote hain.) Physical message: stacking layers thermal path ko gehri karti hai — dekho Thermal Management in ICs.

WHAT: coax formula ko $b$ ke liye invert karo. WHY: yahan sirf oxide thickness ($b$) hi free lever hai, kyunki $a,h,\epsilon$ fixed hain. $C=\frac{2\pi \epsilon h}{\ln (b/a)}$ se shuru karo. Log ke liye solve karo: $\ln (b/a)=\frac{2\pi \epsilon h}{C}.$ $\epsilon =3.45\times 10^{-11}$ F/m, $h=40\times 10^{-6}$ m, $C=35\times 10^{-15}$ F ke saath: $\ln (b/a)=\frac{2\pi (3.45\times 10^{-11})(40\times 10^{-6})}{35\times 10^{-15}}=\frac{8.67\times 10^{-15}}{35\times 10^{-15}}=\mathrm{0.2478.}$ $b=a{e}^{0.2478}=1.5\mu m\times 1.281=1.92\mu m.$ Answer: oxide $b\gtrsim 1.92\mu m$ tak pahunchna chahiye (liner thickness $b-a\approx 0.42\mu m$). Trade-off accept kiya: mota oxide → bada overall TSV diameter → bada keep-out zone jo active silicon chura leta hai, aur fill karna bhi mushkil aur slow. Tumne area aur manufacturability ke badle mein kam capacitance kharidi. Compare karo Chip Packaging constraints se.

WHAT: $N$ nikalo jahan cumulative savings overhead ke barabar ho. WHY: ek shortcut jo use par $\Delta E$ bachata hai tabhi jeetta hai jab total savings one-time cost se zyada ho — classic break-even. Savings per bit-move: $\Delta E=E_{2D}-E_{3D}=3.52\times 10^{-13}-1.52\times 10^{-14}=3.37\times 10^{-13}$ J. Break-even: $N\Delta E=E_{\text{oh}}$ $N=\frac{E_{\text{oh}}}{\Delta E}=\frac{8\times 10^{-13}}{3.37\times 10^{-13}}\approx \mathrm{2.37.}$ Answer: sirf ~3 bit-moves mein yeh pay back ho jaata hai — per-bit saving itni zyada hai is modelled overhead se ki break-even kisi bhi real workload ke liye essentially immediate hai (billions of moves). Insight: high-traffic paths ke liye 3D almost hamesha energetically worth it hota hai; asli limiter thermal rehta hai, payback nahi (dekho Exercises 9–10).

Total power ($Q$ drive karta hai, jo Exercise 9 se $\Delta T$ drive karta hai):

• Option A: $4\times 5=20$ W.
• Option B: $1\times 5+3\times 1=8$ W. Answer: Option B sirf 8 W vs 20 W dissipate karta hai — same footprint mein 12 W (2.5×) kam heat load, toh woh kaafi cooler chalta hai aur kam throttling chahiye. Yahi wajah hai ki real 3D memory-on-logic hota hai. Cooler slow kyun ho sakta hai: Option A mein 4× raw compute hai; agar tum use cool kar sako, toh woh B se zyada compute karta. Lekin ek footprint mein 20 W par buried logic dies overheat ho jaate hain (Exercise 9 ka $\Delta T$ dono $Q$ aur stack thickness $t$ ke saath scale karta hai), clock throttling force hoti hai jo compute advantage mita deti hai. A ko bachane ka tarika: microfluidic (interlayer liquid) cooling — dies ke beech etched channels heat ko stack ke andar se remove karte hain sirf top/bottom se nahi, power ko thermal wall se decouple karte hue. Dekho Thermal Management in ICs aur, is sari density pressure ke historical driver ke liye, Moore's Law.

Ek wire ki delay uski length ke saath ==${\ell }^2$== ki tarah scale karti hai kyunki yeh dono $R\propto \ell$ aur $C\propto \ell$ hoti hai. Coax model mein, oxide outer radius $b$ badhane se $C$ chhhoti ho jaati hai (bada $\ln (b/a)$ denominator). 2D I/O perimeter ki tarah badhta hai ($L$); TSV I/O area ki tarah badhta hai ($L^2$). 3D logic stacking ki asli ceiling heat / power density hai, wire delay nahi.